Fusion Compiler Frontend

Overview

Learn to use Fusion Compiler to perform complete physical synthesis, which is the unification of traditional synthesis and ICCII placement functionality. At the end of the workshop, you will have a design that can be passed on to clock tree synthesis and routing.

Day 1 topics include GUI usage and extensive GUI exercises; Creating the design library and referencing standard cell and IP libraries, reading RTL and dealing with “dirty” or incomplete RTL; Understanding objects, blocks and application options; Details of the seven optimization stages of the compile_fusion flow and the absolute minimum setup required for physical synthesis.

Day 2 covers loading UPF and dealing with incomplete or non-existing UPF; Loading floorplan data and using Fusion Compiler’s advanced auto-floorplanning features; Performing MCMM setup (modes, corners, scenarios), fixing timing setup issues, and accounting for on-chip variation; Configuring concurrent clock and data (CCD) optimization, dealing with macro skew requirements, enabling trial clock tree synthesis (CTS) and performing set up for CTS (non-default routing rules, clock cell selection, etc.)

Day 3 covers how NDM cell libraries are constructed and what source data is required, and how to create a tech-only NDM library for ease of use; Power optimization which includes leakage, dynamic and total power optimization, multibit optimization, clock gate insertion, XOR self-gating and performing trial CTS-based ICG optimization; Various techniques to improve timing and congestion, DesignWare, and pre-route layer estimation technologies. Hierarchical synthesis using abstracts is described in detail.

Objectives

At the end of this workshop you should be able to use Fusion Compiler to:

  • Navigate the Fusion Compiler layout view
    • Control object and layer visibility
    • Select and query layout objects
  • Rearrange panels in the GUI
  • Generate timing histograms
  • Use RTL cross-probing
  • Use help and man to get help and additional information about commands and options
  • Create a design library
  • Read the RTL
  • Manage incomplete RTL
  • Query objects and retrieve design information using attributes
  • Query and set application options to control Fusion Compiler’s behavior
  • Describe the:
    • Unified RTL-to-GDS synthesis and implementation flow
    • Seven stages of compile_fusion
    • Recommended test insertion flow
  • Perform minimum recommended setup steps prior to compile
  • Execute the unified physical synthesis flow
  • Apply the power intent (UPF)
  • Manage RTL-PG constructs
  • Enable Incomplete UPF support
  • Apply a floorplan
  • Configure Fusion Compiler to create a floorplan on-the-fly
  • Perform MCMM setup:
    • Define the corners, modes and scenarios required for
      analysis and optimization
    • Load the MCMM constraints
    • Configure scenario setup
    • Model on-chip variation
  • Handle infeasible timing paths
  • Describe how CCD optimization can improve setup timing
  • Apply CCD controls that limit where and how much useful skew is applied
  • Enable useful skew for macro banks
  • Enable trial CTS to improve CCD results
  • Describe what elements an NDM cell library contains
  • Describe the flows for cell library creation
  • Create an NDM technology-only library for ease-of-use
  • Control leakage, dynamic or total power optimization
  • Use multibit banking
  • Control ICG insertion for dynamic power reduction
  • Invoke ICG optimization to address critical enable pin setup timing
  • Handle spare cells
  • Report and control data path architecture selection
  • Recognize congestion issues and take measures
  • Increase timing optimization effort
  • Control cell density
  • Describe the available layer aware techniques
  • List the steps necessary for top-level implementation
  • Describe what an abstract is and what it contains
  • Describe how to assemble the top-level design

 

Audience Profile

Design engineers who will be using Fusion Compiler to perform Physical Synthesis.
 

Prerequisites

Prior working knowledge of Design Compiler Graphical is expected. Superficial knowledge of ICC II placement is helpful. 
 

Course Outline

Day 1

  • Introduction and GUI use (Lecture + Lab)
  • Reading RTL (Lecture + Lab)
  • Objects, Blocks and App Options (Lecture only)
  • Compile Flows and Minimum Setup (Lecture + Lab)
Day 2
  • Loading UPF and Floorplan (Lecture only)
  • Timing Setup (Lecture + Lab [4+5])
  • CCD Optimization (Lecture + Lab)
Day 3
  • NDM Cell Libraries (Lecture only)
  • Power Optimization (Lecture + Lab)
  • Additional Compile Settings and Techniques (Lecture only)
  • Hierarchical Synthesis (Lecture only)
  • Customer Support (Lecture only)

 

Synopsys Tools Used

  • Fusion Compiler 2019.03-SP2