Design Compiler: Low Power


At the end of this one day, seminar based, workshop you will understand how to apply both traditional and UPF based power optimization techniques during RTL synthesis and scan insertion:

For single voltage designs, you will learn how to apply the 2 traditional power optimization techniques of clock gating and leakage power recovery, optimizing for dynamic power and leakage power respectively.

For multi-voltage or multi-supply designs, you will learn how to apply the IEEE 1801 UPF flow that uses a power intent specification which is applied to RTL designs. You will understand how to synthesize RTL designs for the required power intent and power-optimization requirements using top-down vs. hierarchical UPF methodologies. You will also learn how to insert scan chains to the synthesized netlist ensure that the gate level design does not have any multi-voltage violations, before writing out design data for Place and Route.


At the end of this workshop the student should be able to:

  • Apply clock gating to a design at the RTL and gate level
  • Perform multi-stage, hierarchical, and power driven clock gating
  • Perform leakage optimization using multi Vt libraries
  • Restrict the usage of leaky cells
  • Specify power intent using UPF
  • Demonstrate flexible isolation strategy in UPF 2.0
  • Check for UPF readiness of library, reporting PG pins
  • State the purpose of SCMR attribute in library
  • Recognize tradeoff when using dual vs. single rail special cells
  • Correctly specify PVT requirements
  • State how the 6 special cells are synthesized
  • Describe supply net aware Always on Synthesis
  • Apply 2 key debugging commands in a UPF flow
  • Control voltage, power domain mixing when inserting scan chains
  • Allow/prevent the reuse of level shifters and isolation cells between scan and functional paths
  • Minimize toggle in functional logic during scan shifting
  • Validate SCANDEF information for place and route

Audience Profile

ASIC digital designers, with Design Compiler experience, having need to minimize power consumption in their designs during RTL synthesis and scan insertion.


Experience in synthesizing RTL to gate level design using DC Topographical/Graphical, or have attended the Design Compiler 1 workshop.

Course Outline

Day 1

  • Clock Gating
  • Leakage Power Optimization
  • Power Intent using IEEE 1801 UPF
  • Library Requirements
  • Synthesis with UPF
  • Power Aware DFT

Synopsys Tools Used

The lecture material of this workshop is based on the following Synopsys tools:

  • Design Compiler Topographical 2013.03
  • Power Compiler 2013.03
  • DFT Compiler 2013.03