In this hands-on workshop, you have the choice of either using Fusion Compiler or IC Compiler II to create chip and block-level floorplans using a hierarchical (top-down) design planning approach. The focus is on multi-voltage (UPF) system-on-a-chip (SoC) designs with multiple levels of physical hierarchy, which can contain a mix of multiply-instantiated blocks (MIBs), black boxes, and partial netlists.
- Day 1: gives you a quick overview of the DP flow, and then goes into the details of creating your initial flip-chip layout and performing design exploration to decide on the chip's multi-level physical partitions. You then learn how to split chip level constraints and UPF. You will create block abstracts of the design and move on to automatic shaping of the blocks and voltage areas within the chip.
- Day 2: will cover hierarchical macro and standard cell placement in detail, and cover all options available for macro placement, including congestion and connectivity analysis. We will then cover Pattern-based Power Network Synthesis (PPNS) to design a complex multi-voltage chip-level power network, which is then built for each sub block in an automated and distributed fashion. Power switch insertion is also discussed. Next, the discussion moves to pin placement, including topological constraints and a detailed discussion on feedthroughs.
- Day 3: starts by covering strategies and methods for dealing with blocks, e.g. how to perform ECO changes, how to update constraints or UPF, and how to set up distributed custom scripts. Hierarchical timing estimation and timing budgets, which are used for block implementation, are covered next. Top-level integration and implementation as well as budget shells are then also discussed. The use of black boxes in the design planning flow is woven into the entire workshop.
The lectures are accompanied by extensive hands-on labs.
At the end of this workshop you should be able to use IC Compiler II to:
- Create an NDM design library
- Read the Verilog outlines
- Initialize the chip-level floorplan
- Place the flip-chip bumps
- Place the Signal IO drivers/pads
- Explore the physical design hierarchy
- Commit the physical sub-blocks
- Split full design UPF and timing constraints
- Create placement block abstracts
- Shape and place blocks and voltage areas
- Place macros and standard cells
- Perform connectivity and congestion analysis
- Insert power pads and connect them to the bumps
- Build hierarchically distributed PG rings, meshes and connections for macros and standard cells using Pattern-based Power Network Synthesis
- Insert boundary, end-cap and tap cells
- Insert and connect power switches
- Verify and analyze the power mesh
- Perform pin placement including feedthroughs for all blocks
- Estimate the design's timing to determine feasibility of the design
- Create block budgets for implementation
- Create budget shells for top-level design implementation
- Use black boxes in the design planning flow
ASIC, back-end, or layout designers who will be using Fusion Compiler or IC Compiler II to perform design planning on multi-voltage SoC designs
An understanding of fundamental floorplanning concepts is required. It is assumed that the requirements to create a good floorplan are known.
While prior working knowledge of IC Compiler II or IC Compiler would be very helpful, it is not required. The workshop, however, does assume a basic understanding of ICC II design/timing setup and configuration concepts (corners/modes/scenarios).
- Introduction (Lecture only)
- Initial Design Planning (Lecture + Lab)
- Shaping (Lecture + Lab)
- Placement (Lecture + Lab)
- Build the Power Network (Lecture + Lab)
- Pin placement (Lecture + Lab)
- Block Handling (Lecture + Lab)
- Timing and Budgets (Lecture + Lab)
- Top integration and implementation (Lecture only)
Synopsys Tools Used
- Fusion Compiler 2019.12
- IC Compiler II 2019.12