IC Compiler SoC Design Planning


In this hands-on workshop, you will use IC Compiler to create chip- and block-level floorplans, using a hierarchical (top-down) design planning approach. The focus is on multi-voltage (UPF) system-on-a-chip (SoC) designs, which contain multiply-instantiated macros (MIMs) where the MIMs are initially treated as "black boxes", and are later re-floorplanned as fully-synthesized sub-blocks.

Day 1:  starts with a brief overview of "data setup" for "multi-corner multi-mode" (MCMM) timing analysis, then focuses on the creation of a hierarchical floorplan of a chip-level design with black boxes, including multiply-instantiated macro (MIM) black boxes. This includes a methodology for determining optimum placement of macros and placement blockages.

Day 2: covers Template-based Power Network Synthesis (TPNS) to design a complex multi-voltage chip-level power network, which is "pushed down" into the physical sub-blocks. The hierarchical design-planning flow is then revisited, for a fully-synthesized design (no black boxes): This includes placement and shaping of plan groups (which represent the physical sub-designs) as well as MIMs, and handling voltage areas of a multi-voltage design. "Data Flow Analysis" (DFA) is used to aid in macro array placement.

Day 3: covers the creation of soft macros based on the plan groups. This includes final pin placement and derivation of block-level timing constraints. The soft-macro floorplans are saved in individual libraries so the block can be individually re-synthesized with Design Compiler Topographical, and then "implemented" (placed and routed) in IC Compiler. "On-Demand Loading" (ODL) is introduced to improve floorplanning runtime and memory requirements. Finally, soft-macro floorplans are completed to include power switching (creation of a power switch array, connecting the sleep control, adjusting the power network).

Most lectures are accompanied by a comprehensive hands-on lab.


At the end of this workshop you should be able to use IC Compiler to:

  • Perform multi-corner multi-mode (MCMM) data setup to create an initial design cell, which is ready for design planning, including importing netlists with black boxes
  • Create a hierarchical chip-level floorplan for a multi-voltage SoC design:
    • Define core area and pad cell placement in the periphery area
    • Apply size estimates for black boxes and black box MIMs
    • Create QTMs (Quick Timing Models) for black boxes for chip level timing analysis
    • Define plan groups for sub-designs
    • Create, shape and place the plan groups, as well as voltage areas
    • Determine ideal chip-level placement of black boxes, MIMs and macros
    • Use TPNS to build the physical power network
    • Manual and automatic placement strategies for macros, using "virtual flat placement"
    • Define pin placement of physical sub-designs
  • Use TPNS to perform multi-voltage power network design
    • Create power plan regions
    • Define strategies and templates for rings and meshes
    • Preview and compile the power network
    • Analyze LVS issues and IR drop
    • Push down power structure into blocks
  • Analyze and improve macro placement using DFA
  • Analyze congestion
  • Create soft macros based on the plan groups:
    • Make adjustments to an existing, or add new TPNS strategies to address changes in the floorplan
    • Analyze the power network using the built-in "Network Analysis" feature
    • Perform final pin assignment and analysis on plan groups
    • Analyze timing and perform "place optimization" (IPO) on the top level netlist
    • Create timing budgets for sub-designs
    • "Commit" the plan groups to soft macros
    • Write floorplan files for resynthesis in Design Compiler Topographical and for re-use in IC Compiler
  • Use ODL to reduce floorplanning runtime and memory usage
  • Complete the block-level floorplan:
    • Read and constrain a block level design using information from chip-level floorplanning
    • Create a power switch array, and connect the sleep control
    • Modify a "normal" TPNS template to line up with power switches, and make the necessary modifications to the strategies
    • Understand the pros and cons of using DEF versus Tcl floorplan files for DC-T and ICC
    • Link the top level design with the implemented block level designs

Audience Profile

ASIC, back-end, or layout designers who will be using IC Compiler to perform design planning on multi-voltage SoC designs.


Prior knowledge of IC Compiler is not needed. An understanding of fundamental floorplanning concepts is required. Must be able to use a text editor (vi, vim, emacs) in a UNIX environment.

Course Outline

Day 1

  • Introduction
  • MCMM Data Setup (Lecture)
  • Chip-Level Design Planning with Black Boxes (Lecture + Lab)

Day 2

  • Multi-Voltage Power Network Design (Lecture + Lab)
  • Design Planning with Plan Groups and Voltage Areas (Lecture + Lab)

Day 3

  • Committing Plan Groups to Soft Macros (Lecture + Lab)
  • On-Demand Loading (Lecture)
  • Block-Level Floorplanning (Lecture + Labs)

Synopsys Tools Used

  • IC Compiler 2016.03-SP4
  • IC Validator 2016.06-SP2-4