Physical Implementation

IC Compiler II: Block-level Implementation

Learn to use IC Compiler II to run a complete Place and Route flow on Block-level designs. The flow covered within the course addresses the main design closure steps for multi-voltage designs, with multi-corner multi-mode (MCMM) timing and power challenges.

IC Compiler II: SoC Design Planning

Learn to use IC Compiler II to perform chip-level hierarchical design planning (floorplanning) on multi-voltage (UPF) "System-On-a-Chip" (SoC) designs. The flow includes handling "multiply-instantiated blocks" (MIBs), voltage areas, black boxes, timing budgets and power network design using "Pattern-based Power Network Synthesis" (PPNS).

Fusion Compiler Frontend

Learn to use Fusion Compiler to perform physical synthesis using the compile_fusion command, which unifies traditional synthesis with placement and optimization, along with additional physical design techniques such as concurrent clock and data optimization.

Fusion Compiler Frontend Jumpstart eLearning

This jumpstart will give you an overview of Fusion Compiler frontend features and flow, especially around the compile_fusion command which performs RTL synthesis and placement optimization.