Learn to use IC Compiler II to run a complete Place and Route flow on Block-level designs. The flow covered within the workshop addresses the main design closure steps for multi-voltage designs, with multi-corner multi-mode (MCMM) timing and power challenges.
Learn to use IC Compiler II to perform chip-level hierarchical design planning (floorplanning) on multi-voltage (UPF) "System-On-a-Chip" (SoC) designs. The flow includes handling "multiply-instantiated blocks" (MIBs), voltage areas, black boxes, timing budgets and power network design using "Pattern-based Power Network Synthesis" (PPNS).
Learn to use IC Compiler to perform chip-level hierarchical design planning (floorplanning) on multi-voltage (UPF) “system-on-a-chip” (SoC) designs. The flow includes handling black boxes and “multiply-instantiated macros” (MIMs), in addition to voltage areas. The following design planning features are also covered: “Template-based Power Network Synthesis” (TPNS), ”Data Flow Analysis” (DFA) and “On-Demand Loading” (ODL).