The course will familiarize new students with the FPGA design flow utilizing features of the Synplify Pro product.
This course introduces concepts on full-speed hardware debugging using the Identify toolset which provides an "embedded HDL analyzer".
This course introduces concepts on ASIC prototyping using the Certify ASIC Prototyping tool.
This course shows users the Synphony Model Compiler design flow including model creation, implementation and architectural exploration.
NEW IC Compiler II: SoC Design Planning
NEW Power-Aware Verification with VCS-NLP and UPF
NEW 2016 CES Training Videos
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