The Synopsys SLM Platform is tightly coupled to Synopsys’ industry-leading design implementation, signoff and test solutions, including:
- Links to Synopsys Fusion Design Platform™ for guidance on optimal placement of the monitors and sensors
- Automated and intelligent integration of the monitors and sensors into the RTL or gate-level design provided through the Synopsys TestMAX™ test integration solution
- Direct links with the Fusion Compiler™ RTL-to-GDSII solution to ensure the monitors are integrated while maintaining optimal PPA design metrics
The Synopsys SLM Platform includes several targeted analytics engines that operate on available chip data to enable optimizations at each stage of the semiconductor lifecycle, starting with design implementation, and progressing through manufacturing, production test, bring-up and culminating with in-field operation:
- Links to Synopsys Fusion Design Platform closes the silicon-to-design loop, minimizing required margins and enabling advanced analytics to further optimize design PPA, reliability and silicon predictability
- The SiliconDash™ semiconductor manufacturing analytics engine and the Yield Explorer™ design sensitivity analysis engine use test data enhanced with monitor and sensor data to optimize manufacturing and test operational efficiencies as well as reduce design-related yield limiters
- Synopsys TestMAX ALE Adaptive Learning Engine and Synopsys SLM Embedded Learning Engine enable optimized bring-up and introduce self-analysis as well as safety, security and predictive maintenance capabilities
Rounding out the Synopsys SLM Platform is the hardware IP such as the DesignWare™ PVT Monitors and Sensors (formerly from Moortec) and the traditional SynopsysTestMAX DFT/BIST test IP.
The Synopsys SLM Platform exclusively combines extensive silicon device data and targeted analytics to greatly improve how chips and systems are designed, manufactured, deployed and maintained in the field.