Low Power Webinars

Accelerated Power Analysis and Verification with Synopsys Verdi Technologies

In this webinar, discover how native integrations of Verdi design debug technologies with Synopsys’ power analysis and verification solutions help catch power-related bugs earlier and faster. The industry-leading Verdi platform couples powerful tracing techniques with unique source code and schematic browsers, enabling teams to quickly debug low power issues in RTL or netlist designs, as well as in the UPF power intent specification. These specialized power-aware debug capabilities accelerate low power verification and ensure successful delivery of intended low power features.
Vaishnav Gorur, Product Marketing Manager, Verification Group; Ankush Bagotra, Staff Engineer, Verification Group
Nov 08, 2016
 

 Comprehensive Power Optimization Solution for Faster RTL Signoff (Part 3 of 4)

In this webinar, we will discuss how SpyGlass Power delivers an integrated early power analysis and exploration solution that includes: estimation, profiling, reduction and exploration.
Kiran Vittal, Product Marketing Director, Verification Group; Ken Mason, Corporate Applications Engineer, Verification Group, Synopsys, Inc. 
Sep 21, 2016
 

 Catch low-power simulation bugs earlier and faster with Verdi Power-Aware Debug (Part 2 of 4)

In this webinar, we will demonstrate how Verdi Power-Aware Debug greatly simplifies low-power debug and identifies potential design-killing bugs earlier and faster, with a unified and comprehensive view of the design and its power intent. Specifically, you will learn how visualization of the power architecture can help identify power strategy and connectivity issues upfront; how to use annotated power intent on source code, schematics and waveforms to rapidly root-cause power-related errors back to UPF/RTL; how to debug unexpected design behavior such as Xs caused by incorrect power-up/down sequences etc.
Vaishnav Gorur, Product Marketing Manager, Verification Group; Archie Feng, Corporate Applications Engineer, Verification Group, Synopsys, Inc.
Aug 31, 2016
 

 Addressing Low Power Verification Challenges with Advanced Static Checking and Native Low Power Simulation (Part 1 of 4)

In this session, we will discuss UPF based static and dynamic verification techniques to address these challenges. We will also discuss the problems addressed by Synopsys’ VC LP and VCS NLP tools, to streamline the entire verification process.
Kiran Vittal, Product Marketing Director, Verification Group; Amol Herlekar, Sr. Staff Engineer, Verification Group, Ankush Bagotra, Staff Engineer, Verification Group, Synopsys, Inc. 
Aug 10, 2016
 

 Evolution of Socionext’s Golden UPF Design Flow for Achieving Power Efficiency

Learn about Socionext’s ever-evolving UPF design flow and their experience with successfully deploying a Golden UPF-based methodology using Synopsys tools.
Mahiro Hikita, Manager, Design Department II, SoC Design Division, Socionext, Inc. 
Apr 07, 2016
 

 Evolution of Socionext’s Golden UPF Design Flow for Achieving Power Efficiency (Japanese)

Learn about Socionext’s ever-evolving UPF design flow and their experience with successfully deploying a Golden UPF-based methodology using Synopsys tools.
Mahiro Hikita, Manager, Design Department II, SoC Design Division, Socionext, Inc.
Apr 07, 2016
 

 Synopsys and TSMC Get Smart with Bluetooth for IoT SoCs

Learn about the growing IoT market trends, the required wireless connectivity and new process technologies to achieve low-power consumption and enable efficient connectivity between devices.
Manuel Mota, Technical Marketing Manager, Synopsys; Leon Chang, Program Manager, TSMC
Feb 03, 2016
 

 Securing Your IoT Processor Based System

This webinar will provide insight into IoT edge device security requirements and how they can be met with an ultra-low power processor.
Angela Raucher, Product Line Manager, ARC EM Processors, Synopsys
Dec 03, 2015
 

 Impact of IP Reliability, Functional Safety & Quality in Automotive ADAS SoCs

Learn about ISO 26262 and AEC Q100 standards; latency, power, reliability and process-related design challenges; and how certified IP helps ensure functional safety, reliability and quality management.
Ron DiGiuseppe, Senior Strategic Marketing Manager, Synopsys
Dec 02, 2015
 

 Identifying and Resolving Low Power Issues Before Tapeout

This webinar highlights how to find low power issues during verification using Formality.
Bob Hatt, Staff Corporate Applications Engineer, Synopsys 
Sep 29, 2015
 

 Using Foundation IP in Low-Power 40nm IoT Designs

This webinar will provide details on how foundation IP - logic libraries and embedded memories - can help designers of IoT applications take advantage of the power benefits available in 40nm processes.
Kenneth Brock, Product Marketing Manager, Logic Libraries, Synopsys
Jul 21, 2015
 

 An Approach for Efficient IP Reuse in a Hierarchical UPF Methodology

This webinar will help you understand a Liberty-based approach for effective IP reuse in implementation of a multi-voltage hierarchical design using the IEEE 1801 (UPF) standard.
Viswanath K. Ramanathan, Corporate Applications Engineer, Synopsys; Mary Ann White, Director of Product Marketing, Synopsys
Feb 26, 2015