TCAD Asia Pacific Seminar Series - Taiwan


October 13, 2017                      8:00 a.m. to 4:30 p.m.



Sheraton HsinChu Hotel                 No. 265, Dong Sec. 1, Guangming 6th Rd., Zhubei City, HsinChu County, Taiwan         (Tel) 886 3 620 6000



Seminar Overview

Join our free TCAD Seminar to learn about the application of Synopsys TCAD solutions to accelerate the research, development and optimization of semiconductor technologies. Learn about the latest models and capabilities of the Sentaurus process, device, topography and interconnect simulation tools, the rapidly growing Process Explorer solutions for process integration, and the design-technology co-optimization (DTCO) solutions for advanced logic and memory technology development. 

Who Should Attend

TCAD engineers, technology development engineers, device and process engineers and managers who work in technology development and want to learn the latest techniques for using Sentaurus TCAD products. 

What You Will Learn

The purpose of this seminar is to communicate the latest enhancements in the Synopsys’ TCAD products and their application to the development of state-of-the-art semiconductor technologies. Our aim is to equip attendees with practical techniques to explore new device concepts and to optimize processes to improve device performance and manufacturability. Key topics include TCAD model selection, simulation methods, 3D simulation, 3D emulation, variability analysis and DTCO.


TCAD Overview
The seminar begins with a summary of recent semiconductor technology trends in logic, memory, power management and optoelectronics, and the impact of these trends on TCAD development. We then present an overview of the Synopsys solutions in core TCAD, process emulation, materials modeling and DTCO. This session concludes with a summary of the N-2017.09 release of Sentaurus TCAD, and the Synopsys TCAD roadmap.  

Design-Technology Co-Optimization
This keynote session presents updates of the Synopsys pre-wafer DTCO solution to enable the screening and selection of materials and transistor architecture technology options. We demonstrate the application of DTCO to advanced logic and memory technologies, including the extraction of nominal and variation-aware compact models and parasitic RC extraction.

Topography Simulation
We address the simulation of etching and deposition processes using workflows combining topography, lithography and stress simulation. Applications include high aspect ratio etching in 3D NAND and DRAM and gate etch in advanced FinFET processes. 

Advanced Logic
This session presents the latest Sentaurus TCAD simulation techniques for 7/5/3nm node transistors, including highly scaled FinFET, stacked nanosheets and vertical nanowire FETs. We focus on the modeling of new materials, advanced device transport in the quasi-ballistic regime, quantum transport, variability analysis and NBTI reliability. This session ends with a summary of emerging challenges and solutions in the process integration of advanced logic technologies.

Advanced Memory
This session provides an update on the application of Sentaurus TCAD and Process Explorer to 3D-NAND and DRAM development. We discuss key topics related to the optimization of bit cells, variability analysis, interconnect parasitics, modeling of new materials and process integration. 

Analog / Power ICs
This session provides an overview of the latest applications of Sentaurus TCAD to the development of 90 / 130 / 180nm BCD technologies, including model selection and calibration methodologies. 

Discrete Power Devices
We present updates on simulation of silicon and wide-bandgap power transistors, including recent application examples and updates to material parameters. 


We present the latest enhancements to Sentaurus Device EMW and a new workflow for the simulation CMOS image sensors (CIS). We then introduce a new link between Sentaurus TCAD and RSoft tools for silicon photonics applications. This session ends with an update on the simulation of TFT devices for display applications.