Join our free TCAD Seminar to learn about the application of Synopsys TCAD solutions to accelerate the research, development and optimization of semiconductor technologies. The seminar tracks cover all major semiconductor technologies, from advanced logic and memory to analog, power and optoelectronics. The solutions presented in this seminar are based on the industry-standard Sentaurus TCAD and Process Explorer tools, integrated into simulation flows that often also include the QuantumATK platform for atomic-scale materials modeling and TCAD-to-SPICE extraction for links into circuit simulation.
Who Should Attend
TCAD engineers, technology development engineers, DTCO technologists, device and process engineers and managers who work in technology development and want to learn the latest techniques for using Synopsys TCAD products.
What You Will Learn
The purpose of this seminar is to communicate the latest enhancements in the Synopsys’ TCAD products and their application to the development of state-of-the-art semiconductor technologies. Our aim is to equip attendees with practical techniques to explore new device concepts and to optimize processes to improve device performance and manufacturability. Key topics include solution-oriented TCAD simulation flows, materials modeling, calibration methodologies and model selection, 3D process emulation, variability analysis and DTCO.
The seminar begins with an overview of the major semiconductor industry drivers: AI, IoT, transportation and renewable energy. These drivers create both challenges and opportunities for semiconductor manufacturers who strive to develop new products with the right mix of performance, reliability and cost to service these applications. We then describe semiconductor technology requirements to address these applications and conclude with a summary of the Synopsys TCAD roadmap.
This session presents the latest Sentaurus TCAD techniques for simulating gate-all-around (GAA) transistors. Atomic-scale modeling in QuantumATK of bandstructures in confined channels, contact resistance and conductivity of new metals for middle-of-line (MOL) and back-end-of-line (BEOL) is also presented. Design-Technology Co-Optimization (DTCO) simulation flows that combine TCAD, materials modeling and compact model extraction are illustrated for GAA transistor architectures and process derivatives. This session ends with an outlook for simulating post-CMOS devices based on 2D materials and spintronics.
We present applications of Process Explorer to the process integration and optimization of logic and memory technologies. Use models for extending the detailed 3D models generated by Process Explorer into critical simulation and analysis areas are illustrated through TCAD links between Process Explorer and Sentaurus Interconnect, for stress-modeling, and Sentaurus Topography, for detailed topographical modeling.
This track presents the application of Sentaurus TCAD, Process Explorer, Raphael FX to 3D-NAND and DRAM development, including optimization of bit cells, interconnect parasitic extraction, modeling of leakage currents in dielectric materials and simulation of high aspect ratio etching and deposition. The application of QuantumATK to novel memories is also presented.
Analog / Power ICs
We present calibration methodologies for BCD and IGBT technologies and the extraction of compact models to enable circuit-level simulation of new devices designed in Sentaurus TCAD. We introduce new environments for the optimization of power devices in Sentaurus TCAD and the extraction of circuit netlists from schematic using Custom Compiler. This session ends with updates to the simulation of GaN and SiC power devices.
We describe recent enhancements to Sentaurus Device EMW for optical simulation CMOS image sensor (CIS) and calibration methodologies for the process modeling of CIS. The latest features to support the integration of Sentaurus and RSOFT are demonstrated in the context of Si photonics applications.