The scaling of leading-edge logic technology brings about significant challenges in the scaling and process integration of the interconnect stack, particularly the middle-of-line (MOL) structures. The reduction in metal pitches leads to increased capacitance, while reductions in metal width and height increase the resistance. The resulting RC parasitic contribution to delays can negate or substantially reduce the benefit of improved transistor drive currents. To mitigate the trend of increased resistance, semiconductor manufacturers are exploring alternate metals with lower resistivity than copper.
In the context of DTCO, new interconnect metals not only offer the promise of reduced parasitic loading in the MOL but also enable the integration of new scaling boosters such as buried power rails where low resistivity lines are critical to mitigate IR drop in power distribution networks.
This article presents an overview of the application of atomic-scale modeling with QuantumATK to the study of scaling of interconnect stacks. QuantumATK is capable of computing the electron transport and resistivity of metals using rigorous density functional theory (DFT) and non-equilibrium Green’s function (NEGF) methods. The results and insights derived from the simulations enable technologists to more efficiently select and integrate alternative metals into advanced logic and memory processes.
A typical interconnect stack in shown in Figure 1.