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The scaling of leading-edge logic technology brings about significant challenges in the scaling and process integration of the interconnect stack, particularly the middle-of-line (MOL) structures. The reduction in metal pitches leads to increased capacitance, while reductions in metal width and height increase the resistance. The resulting RC parasitic contribution to delays can negate or substantially reduce the benefit of improved transistor drive currents. To mitigate the trend of increased resistance, semiconductor manufacturers are exploring alternate metals with lower resistivity than copper.
In the context of DTCO, new interconnect metals not only offer the promise of reduced parasitic loading in the MOL but also enable the integration of new scaling boosters such as buried power rails where low resistivity lines are critical to mitigate IR drop in power distribution networks.
This article presents an overview of the application of atomic-scale modeling with QuantumATK to the study of scaling of interconnect stacks. QuantumATK is capable of computing the electron transport and resistivity of metals using rigorous density functional theory (DFT) and non-equilibrium Green’s function (NEGF) methods. The results and insights derived from the simulations enable technologists to more efficiently select and integrate alternative metals into advanced logic and memory processes.
A typical interconnect stack in shown in Figure 1.
Figure 1. Typical interconnect stack
Copper (Cu) is encapsulated by a structure comprised of a liner, which promotes adhesion of the metal, and a barrier layer (typically TaN), which prevents Cu from diffusing into the surrounding dielectric and stops other species like O2, OH – and H2O from entering the interconnect. The resistivity of the Cu increases toward the interface with the liner and the barrier due to increased electron scattering from surfaces, defects and grain boundaries. As linewidths decrease, this surface degradation of the metal conductivity, shown in Figure 2, has a greater impact as it begins to dominate the overall effective resistivity of the wire or the via. Moreover, the thickness of the barrier material must remain approximately constant to protect against electromigration. Since barrier materials have higher resistance than Cu, linewidth scaling further exacerbates the problems since a greater percentage of the cross-sectional area of the wire is made up of the higher resistivity barrier material.
Figure 2: Degradation of the metal (Cu) conductivity due to decreasing linewidths
As demonstrated by publications by GlobalFoundries (GF) and IBM highlighted in this article, atomic-scale simulations with QuantumATK are of paramount importance in characterizing the impact of different scattering effects on the resistance, and in identifying pathways to reduce it.
Density functional theory (DFT) is used to obtain the electronic structure of metal nanowires, such as the density of states and cohesive energy, in order to evaluate their structural integrity and resistance to electromigration. DFT with the non-equilibrium Green’s function (NEGF) module in QuantumATK is used to perform electron transport simulations and obtain electrical and heat currents, resistance/resistivity for various nanowire sizes and orientations, and vertical resistance across interfaces with different liner and barrier materials. DFT+NEGF is also used to evaluate resistance due to various defects and scattering at grain boundaries, and in extracting grain boundary reflection coefficients. The resistivity trends and grain boundary reflection coefficients predicted by QuantumATK are shown to be in good agreement with experiments. QuantumATK also helps with the analysis of barrier materials. DFT+NEB (nudged elastic band) simulations are performed to obtain defect formation energies and activation barriers, which are subsequently used in Sentaurus Process kinetic Monte Carlo simulations to estimate the thickness of the barrier metal needed to avoid diffusion of metal ions into the dielectric layers.
These methods enable the systematic screening and characterization of materials for metal lines with smaller resistance upon scaling than Cu, with smaller via resistance across conductor|liner|barrier|conductor interfaces, and the identification of metals with high cohesive energy so as to forgo the use of diffusion barrier layers. Various metals (Pt, Rh, Ir, Pd, Al, Ru) have been investigated as alternatives to Cu. The authors conclude that Al is not a suitable Cu-replacement conductor due to larger grain boundary (GB) scattering, vertical via resistance and electromigration compared to Cu . Pt, Rh, and Ir nanowires demonstrate superior performance in terms of cohesive energy, i.e. resistance to electromigration, and could be used without diffusion barriers . However, Cu outperforms these metals by having smaller resistance due to GB scattering. Ru is a promising alternative by virtue of it not requiring a diffusion barrier. Surface degradation of Ru from surface defects and GB scattering and resistance across the Ru/liner interfaces were investigated too .
Figure 3: Investigation of Ru as a new conductor metal for interconnect stacks: Ru resistivity as a function of grain diameter
Reducing the resistance by changing liner and barrier materials is another strategy for scaling of interconnect stacks. Calculations suggest that TiN is the most suitable liner for Ru interconnects (compared to Ti or TaN) . It was shown that changing from TaN to Ta barriers for a Cu conductor leads to a significant reduction of the vertical resistance through the via structures, either with Co or Ru wetting layers, as depicted in Figure 4 . This is in agreement with multi-scale studies predicting that by changing from TaN to Ta diffusion barrier for Cu conductors, the via resistance can be reduced by ~26%, which corresponds to a 2% device performance enhancement of the 3 nm technology node . Importantly, oxidation of the barrier (Ta->TaO, Ta2O5) and liner (Ru->RuO2) materials could further increase vertical resistance significantly, varying by as much as an order of magnitude depending on the degree of oxidation and metal-to-metal contact area .
Figure 4: Investigation of different liner (Co and Ru) and barrier (TaN and Ta) materials for interconnect stacks: vertical resistance through the via structures
Knowing how thin the barrier metal should be to prevent conductor metal diffusion in interconnect stacks is also very important, as one could then screen barrier metal materials which can work well at smaller thicknesses, and thus leave more space for the main metal conductor. A study with QuantumATK as part of a multi-scale modeling approach determined that the critical thickness of the TiN layer to prevent Co diffusion within interconnects is 3 nm .
Though most of the work in this area focuses on evaluating electrical via resistance, reducing the thermal resistance is just as important. GlobalFoundries used QuantumATK to calculate the heat current for bulk Cu and Cu/TaN/Co/Cu interfaces and showed that just like the electrical current it is strongly impacted by interface scattering . Results obtained with QuantumATK are then used in large-scale finite element simulations for further modeling of self-heating in interconnects.
In the future we expect that atomic-scale modeling will be applied to the investigation of even more complex metals and materials, for example multi-phase compounds and carbon nanotubes, as the semiconductor industry continues to find pathways to mitigate the rising impact of interconnect parasitics at advanced process nodes.
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