The Evolution of Logic Scaling
Throughout the era of planar CMOS scaling, process nodes retained a physical meaning associated with the minimum critical dimension of the gate length, and scaling advanced through progressive reductions in critical dimensions at a rate governed by Moore’s Law.
Nowadays, scaling of logic process nodes has adopted markedly different characteristics, with process node naming detached from physical dimensions and scaling governed by a different set of factors.
The main reasons for the departure from the traditional scaling of planar CMOS are the rapidly increasing development and manufacturing costs associated with advanced processes, particularly in lithography, and the physical limits that small dimensions present to the realization of properly functioning transistors and interconnects.
Central to the scaling of current and future logic process nodes is the need to evaluate and select technology options based on design-level criteria, embodied in the oft-quoted power, performance, and area (PPA). While the concept of guiding process technology with the goal of achieving certain circuit-level targets is certainly not new, the DTCO methodologies devised to achieve these aims have taken a definitive turn, and the impetus remains to make these methodologies more efficient and adaptable to future requirements.
Candidate technology options for incorporation into new logic process nodes include new transistor architectures and other innovations designed to achieve area gains or reduction in variability, known as scaling boosters, which are often implemented in the middle-of-line (MOL) interconnects. New transistor architectures and scaling boosters are then embodied in new standard cells designs to be evaluated through block-level design experiments. Unavailability of processing lines and engineering wafer cost motivate the use of simulation tools for guide the development, particularly in the early pathfinding phases.