With escalating system-on-chip (SoC) size and complexity, applying verification methods that rely on the writing of directed tests leads to insufficient test coverage because the number of states and test conditions is simply too large to code by hand. SystemVerilog enables new and effective verification methodologies to be deployed, such as constrained random verification that takes advantage of functional coverage technology and compute resources to provide more testing with less test code development. Automated testbenches in SystemVerilog support constrained random and other advanced verification methodologies, providing significant gains in design productivity and minimizing the risks of functional bugs.
SystemVerilog Testbench Assistance services from Synopsys help engineers and designers take full advantage of the SystemVerilog language to build a scalable and reuse-oriented testbench that verifies a device-under-test (DUT) with coveragedriven random stimulus. To ensure a high-quality design environment, Synopsys verification specialists leverage Synopsys’ VCS® verification solution with Universal Verification Methodology (UVM) Standard or the Synopsys and ARM® coauthored Verification Methodology Manual (VMM) for SystemVerilog. Use of UVM helps improve interoperability and makes it easier to reuse verification components.
Figure 1: After initial environment setup, significant productivity gains can be realized with coverage-driven random verification methodology and integration of verification IP into testbenches.
In addition to advancing testbench development, working with Synopsys consultants creates an ideal environment for knowledge sharing, giving verification engineers and designers insight into how to best utilize SystemVerilog’s complete testbench infrastructure, including:
Figure 2: UVM Testbench Architecture
Synopsys’ SystemVerilog Testbench Assistance offers dedicated verification specialists to help:
Synopsys consultants utilize Synopsys’ industry-leading SystemVerilog technology, including VCS’ Native Testbench (NTB) technology that provides built-in native-compiled support for fullfeatured SystemVerilog testbenches as well as the industry’s most comprehensive VIP library. With extensive knowledge of the most advanced verification methodology and more than a hundred successful SystemVerilog testbench deployment engagements, Synopsys is uniquely capable of assisting you to meet your verification environment goals.