DesignWare DDR Memory Interface IP Hardening Services

Highlights

  • Low risk, single source for DDR controllers, PHYs and services
  • DDR experts dedicated to your project success
  • Experience with multiple DDR configurations and technologies
  • Services for PHY hardening or controller and PHY hardening

Overview

With hundreds of DesignWare® DDR Memory Interface IP design wins, Synopsys is best positioned to help with DDR design needs. Our experts provide RTL-to-GDSII services to harden a DesignWare DDR IP core and assist with integration into the System-on-Chip (SoC). Figure 1 illustrates a DesignWare DDR and universal controller implementation. Every design is unique, and with our DDR IP protocol expertise including architecture-to-GDSII we can help you achieve your design goals. 

Figure 1: Synopsys DesignWare DDR IP core implementation

DDR Hardening Services

Synopsys DDR experts will take your unique design inputs (see Figure 1) including DesignWare DDR PHY IP configuration, RTL, IO pad order, block-level and SoC constraints (e.g., target frequency, data/address widths, DDR shape requirements, signal/power/ground ratio and signoff corners) and do the physical design to harden the DDR PHY IP according to your specific SoC requirements. Hardening is split into preliminary and final implementation phases to provide an intermediate review step, allowing appropriate design constraint changes before final implementation.

Figure 2: Synopsys RTL-to-GDSII DDR IP hardening services and deliverables

Additionally, up-to five days of on-site physical design assistance is typically included to help with integration of the DDR PHY into the SoC. Synopsys consultants can also assist with verification of the DDR sub-system.

Other Related Services

In addition to DesignWare DDR memory interface IP hardening services, Synopsys offers a wide range of other services to assist with your design needs, including:

  • DDR PHY signal integrity report service
  • Tape-out assistance
  • Core optimization
  • Tool and methodology consulting
  • Design flow deployment
  • IP integration and SoC verification
  • FPGA-based prototyping

About Professional Services

Synopsys Professional Services assists customers in achieving more than a hundred successful tape-outs every year. These designs span a broad spectrum of applications, chip sizes, complexity and process nodes. This extensive resume enables our consultants to draw upon their valuable experience with the issues and solutions to get a chip to tape-out, helping you to avoid costly delays.

For more information on Synopsys’ complete portfolio of consulting and design services, visit www.synopsys.com/sps or contact your Synopsys sales representative at +1.650.584.5000.

About DesignWare IP

Synopsys is a leading provider of highquality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes logic librariesembedded memoriesembedded testanalog IPwired interface IPwireless interface IPsecurity IPembedded processors, and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys’ IP Accelerated initiative offers IP Prototyping KitsIP Virtual Development Kits and IP subsystems.

Synopsys’ extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.

For more information on DesignWare IP, visit: http://www.synopsys.com/designware. Follow us on Twitter at http://twitter.com/designware_ip.

About Verification IP

Synopsys offers a broad portfolio of Verification IP. All interface and memory titles are included as part of the Synopsys VIP Library and Verification Compiler.

For more information on Synopsys’ complete portfolio of Verification IP, visit http://www.synopsys.com/vip, or contact your Synopsys sales representative at +1.650.584.5000.