SoC Integration & Verification

We help you get better results quicker
and the most out of your SoC design resources.

Synopsys’ SoC Integration & Verification consultants are available to assist in many capacities from concept to GDSII. Whether you just need our guidance, want us to take on a block, or prefer that we take responsibility for the entire SoC, our consultants are ready to perform the full range of design tasks including verification, synthesis, timing, power design, equivalency checking, and constraints generation.

Past customers have taken advantage of our tool, IP, and methodology knowledge to optimize their designs for power, performance, and area. This specialized knowledge comes from our unique perspective as an IP vendor, which gives us insight into both IP integration and low power design.

  • IP Integration: Our role as a leading IP vendor brings unique insights to the challenges of IP integration and allows us to provide specialized know-how on processors, IP, and subsystem building blocks. Our clients rely on our experience with processors, interface IP (DDR, PCIe, USB, HDMI, SATA, Ethernet), embedded memories, logic libraries, and security IP to accelerate their integration process and time-to-market.

    Rather than starting from zero, designers can use DesignWare IP Subsystems and work with our expert consultants to integrate pre-configured SoC-ready subsystems. Synopsys' pre-verified DesignWare® Interface IP SubsystemsARC Data Fusion IP SubsystemARC Sensor & Control IP Subsystem and ARC SoundWave Audio IP Subsystem deliver complete, complex functions that are ready to integrate into a SoC. The DesignWare IP Subsystems and consulting services can cut development times from months to weeks.

  • Low Power Design: Our access to both internal and external IP projects helped us become low power experts. We’ll implement low power design techniques on your designs, all the way from capturing the design’s power intent into UPF, to performing static and functional simulation, equivalency checking, and validation in the physical domain. We’ve minimized power and clock skew through choosing the best clocking schemes, aligning cache memories, and managing both dynamic and leakage power.

Project A3HEEJ: UPF Flow Cuts Power in Half

When the silicon came back for testing, the chip’s power target was found to be off by a factor of two. A subsequent investigation uncovered a one hundred percent simulation-to-silicon correlation error. Pressured to hit a tight market window, the company hired Synopsys Design Services to implement ultra-low power techniques.

Our consultants developed an ultra-low power process. We performed synthesis-through-GDSII tasks, implemented UPF, optimizing clock tree synthesis, and implemented both clock gating and low power modes for SRAMs. In addition, our DesignWare Library group recharacterized Synopsys’s standard cells to a lower power corner.

The new flow cut the simulation-to-silicon correlation error and resulted in a new chip that consumed half the power. The company is developing its next-generation chips using its new low-power flow.

Want to learn how our consultants can help with your SoC integration and verification needs?  

We help you get better results quicker
and the most out of your SoC design resources.