HAPS Datasheets 

Daughter BoardsHAPS Co-Sim & TBV Suite
Add-on ProductsHAPS-DX TBV Suite



HAPS Developer eXpress (HAPS-DX) Series

HAPS-DX Virtex-7 Systems
Uses Xilinx Virtex®-7 FPGAs for capacity up to 4 million ASIC gates. The HAPS-DX Series combines hardware and software automation to make system bring-up go as quickly and easily as possible with a flexible I/O interface architecture to support Synopsys HapsTrak 3 and industry standard FPGA Mezzanine Card (FMC) formats.

HAPS-70 Series

HAPS-70 Virtex-7 Systems
Latest generation of high-performance prototyping systems. The HAPS-70 Series has the most automation, advanced design planning, and SoC validation options on the market today. It uses Xilinx Virtex®-7 FPGAs for capacity up to 144 million ASIC gates.

HAPS-60 Series

HAPS-64 Virtex-6 Systems
The HAPS-64 system is optimized for the highest possible performance. Containing four Xilinx Virtex-6 FPGAs, a single HAPS-64 system can accommodate up to 18 million ASIC gates.

HAPS-62 Virtex-6 Systems
The HAPS-62 system is a high-performance multi-FPGA system containing two Xilinx Virtex-6 FPGAs. A single HAPS-62 system can accommodate up to 9 million ASIC gates; for larger capacity designs the system can be expanded by connecting additional motherboards and/or daughter boards using the HapsTrak standard.

HAPS-61-SP Virtex-6 System
The HAPS-61-SP system is a high-performance single FPGA system containing one Xilinx Virtex-6 FPGA. A single HAPS-61-SP system can accommodate up to 4.5 million ASIC gates.

Daughter Boards

Interfaces supporting standard protocols

iconRISER8_MGB Board
The HAPS® RISER8 Multi-Gigabit Board (MGB) is a right-angled eight-lane connector to ease connection of MGB boards to HAPS prototyping systems. Supports existing HAPS MGB interface boards such as QSFPPLUS_MGB, PCIE-4_MGB, SATA-4_MGB, and ETH-4_MGB.

iconGPIO Interface Board
The HAPS® General Purpose I/O (GPIO) is a multi-purpose interface debug board used to access internal FPGA signals on the HAPS prototyping system. The GPIO_HT3 board can be set up for specific debug interfaces with an ARM debug, 3.3V GPIO, VCCO-level GPIO, micro-USB port, serial LCD, buttons, LEDs, and single-ended and differential clock connectors.

iconQSFP+ Interface Board
The HAPS® QSFP+ is a dual 4-channel QSFP+ high speed transceiver interface board that supports up to eight high speed serial links at 10 Gbps per link. With the use of off-the-shelf adapter modules, this high speed transceiver board can support many protocols, such as QSFP+, SFP+, CX4, 40G Ethernet, 10G Ethernet, SAS and others.

LAI_HT3 Daughter Board
The HAPS® Logic Analyzer Interface (LAI_HT3) board allows probing of dedicated signals with standard Logic Analyzers. The LAI_HT3 is a pass-through board for all power and I/O signals passing through a single HapsTrak 3 connector on a HAPS system.

The USB3_HTII is a HAPS daughter board providing a single port USB 3.0 physical layer interface. The daughter board supports USB 3.0 Device operation when utilized alongside the DesignWare USB 3.0 digital controller IP (sold separately) or other 3rd party controller IP.

High Speed I/O Virtex-6LXT Daughter Board
The High Speed IO Virtex-6LXT daughter board allows high speed interface standards such as PCIe Gen 2, SATA 6 Gbps, and Gigabit Ethernet to interface with the HAPS-60 or HAPS-50 systems. The High-Speed I/O board can be connected to the HAPS-60 series or HAPS-50 series systems as a daughter board through two standard HapsTrak II connectors. The High Speed IO board features the Xilinx Virtex-6 XC6VLX75T FPGA which includes 12 GTX transceivers to enable the support for high speed interfaces.

Memory Types

FLASH_1x1_HTII Daughter Board
The FLASH_1x1_HTII HAPS daughter board contains two 1Gbit NOR Flash PROMs, accessible as 8-bit or 16-bit wide words.

DDR2_1x2_SODIMM_HTII Daughter Board
The DDR2_1x2_SODIMM_HTII daughter board is a 200-pin SODIMM DDR2_SDRAM module that allows chip developers to interface ASIC/SOC designs with an external high capacity and high performance DDR2 memory module using HapsTrak II connectors used with the HAPS-60 series.

The SRAM_1x1_HTII board contains a synchronous SRAM subsystem. The memory is organized in 2Mx72bits. The default operation mode is Pipeline.

Interconnect System Components
HAPS to HAPS accessories

HapsTrak 3 Interconnect Board
The HAPS® CON_HT3 interconnect board aids in the building of point-to-point connections between two FPGAs in the HAPS prototyping system. The CON_HT3 board connects 48 user I/O signals while power pins are disconnected.

External Clock Distribution Board
The HAPS® External Clock Distribution Board (ECDB) extends direct synchronization of clocks to connect or interface up to six HAPS systems together. The HAPS ECDB automatically replicates input clocks to the output clocks to support up to twelve clocks across six HAPS-60 or HAPS-70 systems capable of supporting up to 288M ASIC gates.

The BIO1 contains LED indicators, push buttons and a USB port to support direct access to the design for debug purposes. The card is controlled via a GPIO header on a HAPS motherboard. Several BIO1 cards can be stacked together side-by-side to expand the number of I/O functions.

LAB_1x1A Daughter Board
The LAB_1x1A is perfect for small hand-built experiment designs, and also provides easy access to measure points for all signals in a HapsTrak II connector. The signals from the HapsTrak II connector are evenly spread out in two areas, one with a 2 mm grid and the other with a 0.1" grid.

STB2_1x1 Test Board
The STB2_1x1 is a board for testing purposes, used in combination with the self-tests for motherboards in the HAPS-50 series. With STB2_1x1, it is possible to detect open circuits as well as power and ground faults in any HapsTrak II connector.

Interface HAPS to other systems

The MICT_1x1 board makes all signals in one HAPS connector available in four 38-pin Mictor connectors for easy access with a logic analyzer. It can be placed directly on the HAPS motherboard or stacked on a daughter board.

HAPS Deep Trace Debug
High-capacity debug storage for HAPS

HAPS Deep Trace Debug System
HAPS Deep Trace Debug (DTD) System contains a HAPS-DX7 system, cables, and interface accessories to enable high-capacity debug of an ASIC design partitioned across up to 4 FPGAs of a HAPS-70 system. The system establishes electrical connections between a HAPS-70 system and the HAPS-DX system which serves as the debug control and storage system.

HAPS Deep Trace Debug 4-FPGA Kit
HAPS Deep Trace Debug (DTD) 4-FPGA Kit contains cables and interface accessories to enable high-capacity debug of an ASIC design partitioned across up to 4 FPGAs of a HAPS-70 system. The kit establishes the electrical connections to a HAPS-DX system which serves as the debug control and storage system for the HAPS-70 system.

HAPS Deep Trace Debug 4-FPGA Add-On Pack
HAPS Deep Trace Debug (DTD) 4-FPGA Add-On Pack is an optional add-on for the HAPS DTD 4-FPGA Kit (sold separately). It contains cables and interface accessories to incrementally add up to 4 more FPGAs, maximum of 8, to a multi-FPGA HAPS DTD scenario. The add-on pack establishes the electrical connections to a HAPS-DX system which serves as the debug control and storage system for the HAPS-70 system.

Add-on Products

Includes Universal Multi-Resource Bus (UMRBus) for host workstation connectivity to HAPS and IP for co-simulation or transaction-based verification with HAPS.

HAPS UMRBus Interface Kit
The HAPS UMRBus (Universal Multi-Resource Bus) Interface kit is a complete and reliable set of components that allow bi-directional data exchange (at runtime) between software (C/C++ or Tcl/TK applications) and hardware (DUT).


ProtoCompiler – Design and Debug Automation for the HAPS Series
HAPS Co-Sim & TBV Suite – Co-Simulation and Transaction-Based Validation Suite
HAPS-DX TBV Suite – Transaction-Based Validation Suite for the HAPS-DX Series

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