|Who Pays for EDA Shift Left?|
The industry is changing and more information is flying around at an ever-faster pace. It is intended to reduce costs for semiconductor companies, but who is footing the bill?
Feb 12, 2015
|With Responsibility Comes Power|
Who is responsible for ensuring a chip is within its power budget and are they being given the tools to do the job?
Feb 12, 2015
|IP Power Models Enable Energy-Aware System-Level Design|
The way a platform is used determines how much energy it consumes, requiring a holistic approach to energy management. Energy efficiency is one of the primary design metrics for heterogeneous multi-core mobile platforms, and the very real threat of dark silicon reinforces the fact that we must manage energy consumption in these platforms intelligently.
Dec 04, 2014
|Are More Cores Really Better?|
The effects of one architectural change on hardware, software and the design flow have far-reaching consequences. Adding a second processing core adds untold complexity.
Nov 06, 2014
|Raising the Abstraction of Power: Trends |
Given that design requirements for today’s SoCs go well beyond performance and area, energy efficiency and its impact on system design plays a major role for many end applications ranging from wireless sensor networks to autonomous vehicles as well as emerging applications in the Internet of Things market segment, where cooling capability is limited and expensive.
Jul 10, 2014
|S-L Power Modeling Gains Steam |
A system-level power model would enable power architecture planning. EDA, IP and systems companies are coming together to determine where to go next.
Jun 12, 2014
|Non-separation of Power and Performance|
How much power does a system consume? The simplistic path to power estimation for a system used to be tossing a few metrics – standby, typical, worst case, with figures pulled from a datasheet, simulation, or physical measurement – into a spreadsheet. After filling the remaining holes with SWAG (scientific wild-ass guesses), and summing things up, there was a bottom line.
Jun 04, 2014
|Architecting for Efficiency|
To design an SoC most efficiently, there are many considerations to keep in mind. By definition, to be efficient is to perform or function in the best possible manner with the least waste of time and effort; having and using requisite knowledge, skill, and industry. As this relates to SoC design today, achieving the highest level of efficiency is a challenge with many dimensions.
Apr 10, 2014
|Synopsys’ ESL Power Analysis|
This article addresses the question, "what tools or methods do architects and developers have or should have to define a realistic power budget at the system level?" System-level tools for power-aware virtual prototyping and power-efficient programmable hardware design are available today, enabling architects and developers to define realistic power budgets for their SoC hardware and software much earlier in the development cycle.
Mar 18, 2014
|New Architectures Redefining the Data Center|
Different software approaches and more granularity in processing are changing information technology. The cost of powering and cooling data centers, coupled with a better understanding of how enterprise-level applications can utilize hardware more effectively, are spawning a new wave of changes inside of data centers.
Sep 26, 2013
|Hardware Accelerators Earn Their Keep|
Hardware accelerators have been used for years, but with the proliferation of multicore chips and SoCs their use is evolving. Multicore processors have reduced the reliance on hardware accelerators, but that doesn't mean the number of hardware accelerators is shrinking.
Aug 01, 2013
|Achieving Performance Verification of ARM-Processor-based SoCs|
Verification IP is a critical component of any SoC functional verification strategy. However, now, instead of just giving you exceptional functional coverage, Synopsys Discovery VIP can also give exceptional coverage for performance verification.
Jul 31, 2013
|You can tune a piano, but you can't tune a cache without help|
Why protocol analysis is important in the system architecture and verification process – not just during the design of compliant IP blocks – and what to look for in performance verification of an SoC design.
May 30, 2013
|30 years of DSP: From a child's toy to 4G and beyond|
Dec 18, 2011, marked the 25th anniversary of EDA provider Synopsys Inc, which has been both witness to and participant in the evolution of signal processing.
Aug 27, 2012
|Early Optimization of Multicore SoC Architectures Using System-level Design Methods and NoC Interconnect Technology|
Learn how one can use system-level design methods at the earliest stages of SoC design to determine the optimal interconnect configuration that meets a set of performance goals and system constraints. With a system-level environment like Synopsys Platform Architect and configurable SoC interconnect IP like Arteris FlexNoC, it is possible to quickly create and run multiple simulations that explore and optimize possible configurations.
Aug 20, 2012
|Software Agnostic Approaches to Explore Pre-silicon System Performance|
A new modeling methodology is proposed to improve performance validation at an early stage in the design cycle of systems dedicated to handheld devices. Hardware models are typically available early in the chipset development cycle, but software, such as multimedia applications, may not be developed until after the ASIC is designed. An alternative source of simulation stimulus must be found so that hardware models can be exercised in the absence of such software. This paper describes three approaches that overcome this dependency and enable the validation of application processor performance at the architecture stage of silicon design: high-level software models, trace-driven characterization, and statistical traffic models. Correlation between actual measurements and simulation outputs demonstrates that these methods provide adequate accuracy for performance validation.
May 22, 2012
|Virtual Platforms: Breaking New Grounds|
The case for developing and using virtual platforms (VPs) has now been made. If developers of complex HW/SW systems are not using VPs for their current design, complexity of next generation designs demands for their adoption. This paper summarizes a special session focused on the latest applications and latest use cases for VPs. It gives an overview of where this technology is going and the impact on complex system design and verification.
May 22, 2012
|IEEE Approves Revised IEEE 1666™ "SystemC Language" Standard|
IEEE announced that the IEEE Standards Association (IEEE-SA) Standards Board has approved a revised version of the IEEE 1666™ "Standard SystemC Language Reference Manual," which specifies SystemC, the high-level design language used in the design and development of electronic systems. The new version of IEEE 1666 encompasses many enhancements, notably the support for transaction-level modeling (TLM), a critical approach to enable higher level and more efficient design of complex integrated circuits (ICs) and system-on-chips (SoCs).
Nov 10, 2011
|Platform Architect MCO is EDN Hot Product of 2011|
Synopsys' Multicore Optimization Technology is EDN's hot product of 2011. This technology is meant for performance analysis and early definition of multicore system architectures in SystemC. With Multicore Optimization Technology, users of of Platform Architect can capture HW/SW performance models of multicore system architectures in the early concept phase for robust performance measurement and trade-off analysis, months prior to software availability.
Nov 08, 2011
|Optimizing Multicore System Performance|
Multicore Optimization technology, part of Platform Architect, enables design teams to more accurately predict system performance using SystemC months before software is available.
Jun 22, 2011
|Using the application modeling and mapping methodology for system-level performance analysis|
This article describes our experiences using the Application Modeling and Mapping methodology (AMM) based on commercial tooling from Synopsys. This methodology is valuable at the technical and organizational level for investigating the feasibility of new electronic products.
Sep 26, 2010
|Get an optimized flow on an AMBA-based design|
CoWare announced the availability of a new interconnect and memory-subsystem performance optimization design flow for its Platform Architect product.
Jun 15, 2009
|ESL Methods for Optimizing a Multi-media Phone Chip|
Our team is chartered to validate and optimize the architecture of our NXP mobile phone chips. This is a very challenging application domain, as an ever increasing set of multi-media and wireless communication functions need to be integrated into one SoC.
May 27, 2008