Tool Used: OptSim
This example demonstrates the functioning of an advanced Bitrate Discrimination Circuit (BDC) based dual-rate burstmode receiver.
Bitrate Discrimination Circuit (BDC) based burstmode receiver using SPICE cosimulation in OptSim. This example is based on the Burst-mode receiver model reported in the paper in [1] ("Burst-mode Bit-rate Discrimination Circuit for 1.25/10.3-Gbit/s Dual-rate PON Systems" by Kazutaka Hara, Shunji Kimura, Hirotaka Nakamura, Naoto Yoshimoto, and Kiyomi Kumozaki). It basically demonstrates the functioning of an advanced Bitrate Discrimination Circuit (BDC) based dual-rate burstmode receiver that can be used to detect a time-division multiplexed composite burstmode signal with dual bitrates and separate out the data bursts of each bitrate. A data burst is typically made of a preamble, which consists of a known sequence of data bits followed by the actual payload. The BDC-based burstmode receiver makes use of the unique preamble sequence sent at the start of each burst signal to implement a logic that generates a gate signal for transmitting that particular burst through.
The main block in this receiver is the Burstmode-Bitrate Discrimination Circuit (B-BDC), which is made up of two BDC circuits, one for each bitrate. The block diagram of the B-BDC circuit is shown below:
The figure below shows the block diagram of Burstmode-Bitrate Discrimination Circuit (B-BDC) unit [1]