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Jitter is a measure of short-term, significant variations of a digital signal from its ideal position in time. If these variations are very slow (within 10 Hz as per the International Telecommunication Union), they are known as wander. Jitter affects the extraction of clock and network timing. Although receivers in OptSim™ do not use clock and data recovery (CDR) circuits, it is possible to analyze jitter-induced penalties using OptSim. The three main sources of jitter are: (i) system-related sources such as crosstalk, dispersion, and reflections/interference; (ii) data-dependent sources such as intersymbol interference and duty-cycle distortion; and (iii) random noise in the system .
Total jitter at a given BER is an important performance metric for high-speed serial I/O links. It is possible to estimate total jitter using bathtub curves, as discussed in the October 2016 issue of the RSoft enews .
This article demonstrates how to use the electrical jitter model  in OptSim to simulate random and deterministic parts of the total jitter.
OptSim’s Electrical Jitter Model
OptSim’s electrical jitter model adds jitter on an electrical signal. This is very useful, for instance, in simulating clock jitter. As we know, the clock jitter results in time-deviation of the sampling instant.
For analysis purposes, this effect can be modeled by skewing the electrical signal before the measurement component and considering an ideal clock that is not jittered.
As shown in Figure 1, the electrical jitter model changes the position of the electrical signal samples as if it were sampled by a jittered clock.
Figure 1. Functioning of the electrical jitter model
On each period, the input electrical signal is twisted according to the value of the jitter signal amplitude multiplied by the jitter factor k_jitter, which is a user-specified parameter. Applied twist is jitter signal amplitude times the “k_jitter” parameter.
Figure 2 shows input and output signals for the electrical jitter model.
Figure 2. Input and output signals at the electrical jitter model
To simulate deterministic and random parts of the total jitter, you can use a setup as shown on the left side of Figure 3.
Figure 3. Setup for the deterministic and random parts of the total electrical clock jitter
Deterministic and random inputs are gated through two multiplier blocks acting as switches whose on and off states are decided by whether the dc input is 1 or 0, respectively.
We will create a test example to see the effect of jitter modulation at the receiver section.
A single RZ channel at 10 Gb/sec is transmitted over 120 Km of a singlemode fiber (SMF). The fiber dispersion is partially compensated through an additional 18 Km of a dispersion compensating fiber (DCF) with a 75% dispersion compensation ratio. The signal is preamplified by an EDFA booster with a noise figure F = 4.5 dB. The average launch power is 0 dBm. The accumulated fiber attenuation is completely compensated using an erbium-doped fiber amplifier (EDFA) preamplifier with F= 4.5 dB.
A sensitivity receiver detects the channel. After the detector, an electrical jitter block is placed to simulate jitter modulation. The jitter block is driven by an electrical-wave generator compound component (CC) as shown on the left-hand side of Figure 3. A parametric run allows you to analyze system performance with different jitter conditions.
The topology of the test example is shown in Figure 4.
Figure 4. Topology of the test setup
The first run simulates an ideal clock that has no jitter for the receiver. The resulting eye diagram at the receiver is widely opened (top left, Figure 5). The second and third run introduces a deterministic sinusoidal modulated jitter (lower left and lower right, Figure 5). In particular for the second run (lower left, Figure 5), the jitter is kept low and in the third run (lower right, Figure 5), the amplitude of the input jitter signal is increased in order to enhance the jitter effect. The last two runs introduce a random jitter (upper right, Figure 5). In this case of random jitter, the modulated signal is obtained through a noise Gaussian generator followed by a Bessel filter.
Figure 5. Received eye for different amounts of deterministic and random jitter
The setup is such that at the receiver section, the evaluated Q factor (optimum threshold) does not change significantly introducing jitter . On the other hand, we can verify that the receiver is more susceptible to the possible sampling time variations in presence of jitter as shown in the " Eye closure vs. Sampling Instant" chart in Figure 6.
Figure 6. Eye closure sensitivity to two different amounts of jitter modulation
As we can see, the electrical jitter model in OptSim is very useful for simulating jitter in the timing clock, in understanding the effects of jitter modulation, and in evaluating the receiver’s eye closure sensitivity to both deterministic and random jitter. For more information, please contact email@example.com
1. Hancock, J., “Jitter – Understanding it, Measuring it, Eliminating it Part 1: Jitter Fundamentals,” High Frequency Electronics, 2004, http://www.highfrequencyelectronics.com/Apr04/HFE0404_Hancock.pdf.
The Synopsys Photonic Solutions team is launching a new series of webinars to highlight the complete value chain for creating PIC designs, demonstrate the latest Synopsys PIC Design Suite updates, and guide you through hands-on application examples.
You will learn how to design and simulate datacom and sensing PICs using the advanced capabilities and seamless interfaces of Synopsys’ PIC Design Suite tools, including:
July 31, 2019
PIC Design Suite from Idea to Fabrication
August 12-16, 2019
Simulation Methodology for LiDAR On-Chip
August 26-30, 2019
Design and Optimization of Photonic Components
Sept. 9-13, 2019
Design and Layout of a 400G Polarization-Multiplexed Coherent Transmitter and Receiver Photonic Integrated Circuit
By the end of this series, you will have experienced the complete PIC Design Suite value chain. You will have learned to develop PIC concepts from design intent to mask layout for fabrication compatible with a range of PIC materials (SiPh, InP, SiN, etc.) available in the Synopsys material library.
Interested in learning more? Contact us at: firstname.lastname@example.org
The HHI Process Design Kit (PDK) for InP photonics is a licensed plug-in library for OptoDesigner. The design kit supports multi-project wafer (MPW) runs provided by Fraunhofer HHI via the technology broker JePPIX, in direct commercial collaboration with Fraunhofer HHI. The design kit contains the standard OptoDesigner library as well as HHI-specific information such as mask layer names, design rules, and GDS settings.
The material layer on this PDK has been updated to ensure BB/BB overlap is flagged by the DRC.
PDK SMART Photonics
SMART Photonics is the first foundry to offer a commercial, generic process for producing InP-based PICs. The SMART Photonics PDK has a comprehensive building block library consisting of active and passive devices. The PDK evolved from the COBRA PDK that has been extensively tested by many universities, research institutes, and industrial partners in various MPW runs over the last several years.
This PDK is a plug-in library for our PIC Design Suite, bi-directional layout generation and verification and circuit simulation.
In addition to the photonic elements from the standard OptoDesigner library, the PDK contains technology-specific information such as mask layer names, design rules, validated building blocks, die sizes, and GDS file settings.
On July 16, 2019, Synopsys Photonic Solutions and Tower Semiconductor hosted two webinar sessions on the design of a QPSK transceiver for the PH18 Tower open foundry silicon photonics process. More than 120 people registered for the webinars.
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