Quick Tip: Modeling Deterministic and Random Electrical Jitter in OptSim

Jitter is a measure of short-term, significant variations of a digital signal from its ideal position in time. If these variations are very slow (within 10 Hz as per the International Telecommunication Union), they are known as wander. Jitter affects the extraction of clock and network timing. Although receivers in OptSim™ do not use clock and data recovery (CDR) circuits, it is possible to analyze jitter-induced penalties using OptSim. The three main sources of jitter are: (i) system-related sources such as crosstalk, dispersion, and reflections/interference; (ii) data-dependent sources such as intersymbol interference and duty-cycle distortion; and (iii) random noise in the system [1].

Total jitter at a given BER is an important performance metric for high-speed serial I/O links. It is possible to estimate total jitter using bathtub curves, as discussed in the October 2016 issue of the RSoft enews [2].

This article demonstrates how to use the electrical jitter model [3] in OptSim to simulate random and deterministic parts of the total jitter.

OptSim’s Electrical Jitter Model

OptSim’s electrical jitter model adds jitter on an electrical signal. This is very useful, for instance, in simulating clock jitter. As we know, the clock jitter results in time-deviation of the sampling instant.
For analysis purposes, this effect can be modeled by skewing the electrical signal before the measurement component and considering an ideal clock that is not jittered.

As shown in Figure 1, the electrical jitter model changes the position of the electrical signal samples as if it were sampled by a jittered clock.

Figure 1. Functioning of the electrical jitter model

On each period, the input electrical signal is twisted according to the value of the jitter signal amplitude multiplied by the jitter factor k_jitter, which is a user-specified parameter. Applied twist is jitter signal amplitude times the “k_jitter” parameter.

Figure 2 shows input and output signals for the electrical jitter model.

Figure 2. Input and output signals at the electrical jitter model

Setup for Introducing Deterministic and Random Jitter

To simulate deterministic and random parts of the total jitter, you can use a setup as shown on the left side of Figure 3.

Figure 3. Setup for the deterministic and random parts of the total electrical clock jitter

Deterministic and random inputs are gated through two multiplier blocks acting as switches whose on and off states are decided by whether the dc input is 1 or 0, respectively.

Setup for the Test Example and Results

We will create a test example to see the effect of jitter modulation at the receiver section.

A single RZ channel at 10 Gb/sec is transmitted over 120 Km of a singlemode fiber (SMF). The fiber dispersion is partially compensated through an additional 18 Km of a dispersion compensating fiber (DCF) with a 75% dispersion compensation ratio. The signal is preamplified by an EDFA booster with a noise figure F = 4.5 dB.  The average launch power is 0 dBm. The accumulated fiber attenuation is completely compensated using an erbium-doped fiber amplifier (EDFA) preamplifier with F= 4.5 dB.

A sensitivity receiver detects the channel. After the detector, an electrical jitter block is placed to simulate jitter modulation. The jitter block is driven by an electrical-wave generator compound component (CC) as shown on the left-hand side of Figure 3. A parametric run allows you to analyze system performance with different jitter conditions.

The topology of the test example is shown in Figure 4.

Figure 4. Topology of the test setup

The first run simulates an ideal clock that has no jitter for the receiver. The resulting eye diagram at the receiver is widely opened (top left, Figure 5). The second and third run introduces a deterministic sinusoidal modulated jitter (lower left and lower right, Figure 5). In particular for the second run (lower left, Figure 5), the jitter is kept low and in the third run (lower right, Figure 5), the amplitude of the input jitter signal is increased in order to enhance the jitter effect. The last two runs introduce a random jitter (upper right, Figure 5). In this case of random jitter, the modulated signal is obtained through a noise Gaussian generator followed by a Bessel filter.

Figure 5. Received eye for different amounts of deterministic and random jitter

The setup is such that at the receiver section, the evaluated Q factor (optimum threshold) does not change significantly introducing jitter . On the other hand, we can verify that the receiver is more susceptible to the possible sampling time variations in presence of jitter as shown in the " Eye closure vs.  Sampling Instant" chart in Figure 6.

Figure 6. Eye closure sensitivity to two different amounts of jitter modulation

As we can see, the electrical jitter model in OptSim is very useful for simulating jitter in the timing clock, in understanding the effects of jitter modulation, and in evaluating the receiver’s eye closure sensitivity to both deterministic and random jitter. For more information, please contact rsoft_support@synopsys.com

References:

1.       Hancock, J., “Jitter – Understanding it, Measuring it, Eliminating it Part 1: Jitter Fundamentals,” High Frequency Electronics, 2004, http://www.highfrequencyelectronics.com/Apr04/HFE0404_Hancock.pdf.

New Photonic Solutions Webinar Series

The Synopsys Photonic Solutions team is launching a new series of webinars to highlight the complete value chain for creating PIC designs, demonstrate the latest Synopsys PIC Design Suite updates, and guide you through hands-on application examples.

You will learn how to design and simulate datacom and sensing PICs using the advanced capabilities and seamless interfaces of Synopsys’ PIC Design Suite tools, including:

• Circuit simulation
• Layout generation and verification
• Component simulation

Webinar Schedule:

 Webinar Topic July 31, 2019 PIC Design Suite from Idea to Fabrication August 12-16, 2019 Simulation Methodology for LiDAR On-Chip August 26-30, 2019 Design and Optimization of Photonic Components Sept. 9-13, 2019 Design and Layout of a 400G Polarization-Multiplexed Coherent Transmitter and Receiver Photonic Integrated Circuit

• PIC Design Suite from Idea to Fabrication: Provides participants with an overview of the Synopsys PIC Design Suite and the value of using the complete design value chain for your PIC ideas.
• Simulation Methodology for LiDAR On-Chip: Demonstrates our methodology for designing a LiDAR chip with the RSoft device tools, including BeamPROP and FullWAVE.
• Design and Optimization of Photonic Components: Covers photonic device optimization, including a design flow with verification using tools such as BeamPROP (BPM), FullWAVE (FDTD) and ModePROP (EME).
• Design and Layout of a 400G Polarization-Multiplexed Coherent Transceiver PIC: Focuses on photonic system and layout tools, including the comprehensive, bi-directional interface between OptSim Circuit and OptoDesigner.

By the end of this series, you will have experienced the complete PIC Design Suite value chain. You will have learned to develop PIC concepts from design intent to mask layout for fabrication compatible with a range of PIC materials (SiPh, InP, SiN, etc.) available in the Synopsys material library.

PDK Updates: InP Technology Platforms Fraunhofer HHI and SMART Photonics PDKs

The HHI Process Design Kit (PDK) for InP photonics is a licensed plug-in library for OptoDesigner. The design kit supports multi-project wafer (MPW) runs provided by Fraunhofer HHI via the technology broker JePPIX, in direct commercial collaboration with Fraunhofer HHI. The design kit contains the standard OptoDesigner library as well as HHI-specific information such as mask layer names, design rules, and GDS settings.

The material layer on this PDK has been updated to ensure BB/BB overlap is flagged by the DRC.

PDK SMART Photonics

SMART Photonics is the first foundry to offer a commercial, generic process for producing InP-based PICs. The SMART Photonics PDK has a comprehensive building block library consisting of active and passive devices. The PDK evolved from the COBRA PDK that has been extensively tested by many universities, research institutes, and industrial partners in various MPW runs over the last several years.

This PDK is a plug-in library for our PIC Design Suite, bi-directional layout generation and verification and circuit simulation.

In addition to the photonic elements from the standard OptoDesigner library, the PDK contains technology-specific information such as mask layer names, design rules, validated building blocks, die sizes, and GDS file settings.

• The DRC check of pad spacing to uncoated facet was implemented and tested for various packaging. The DRC now checks for 100um distance to coated facet and >= 10um for an uncoated facet. This is to avoid false DRC errors to top and bottom facets where there is no coating.
• The SMART photonics PDK includes several available die sizes. The die template size described by “cbDie’ was updated to support additional optical ports for the 8mm size dies.

Review: Highlights from the TowerJazz Open Foundry Silicon Photonics Process Webinar

On July 16, 2019, Synopsys Photonic Solutions and Tower Semiconductor hosted two webinar sessions on the design of a QPSK transceiver for the PH18 Tower open foundry silicon photonics process. More than 120 people registered for the webinars.

Webinar topic highlights:

• Dr. Samir Chaudhry, Director of Design Enablement, introduced the Tower PDK, process technology, and Tower MPW service. Tower PDKs are available in both OptSim Circuit and OptoDesigner.
• Synopsys introduced our PIC design tools for a seamless manufacturing flow that does not require any additional third-party software.
• Dr. Bowen Wang, Senior Application Engineer at Synopsys, performed a live design and simulation example of a QPSK transceiver in TowerJazz’s PDK. The design and simulation were divided as follows:
• Circuit design of the transmitter using OptSim Circuit, then layout generation and verification with Design Rule Checks for the implemented layout in OptoDesigner.
• Circuit design of the receiver part and layout generation and verification with OptoDesigner.
• Merging of the transmitter and receiver PICs in the circuit tool OptSim Circuit for simulation by adding data generator, external laser and measurement blocks to check frequency response, constellation diagram and eye diagram.
• Validation with Synopsys IC Validator that compares the netlist generated from the schematic design in the circuit simulator and the annotated GDS/netlist generated in OptoDesigner with the Layout vs Schematic (LVS) feature, which also contains the parameters of the functional components which are expected to be checked.

Webinar Q&A highlights:

• Can users use user-defined components in this flow and combine them with the Tower Semiconductor PDK?
Answer: Yes, it is fully supported in this flow. Users can design components with Synopsys device tools such as RSoft and Sentaurus TCAD. With the PDK Utility, the generated S-matrix and layout information can be imported into OptSim Circuit and OptoDesigner.
• Is the bi-directional interface available in the current Tower Semiconductor PDK?
Answer: Yes, in this webinar we only showed the flow from OptSim Circuit to OptoDesigner. The flow from OptoDesigner to OptSim Circuit is available. You can use that feature, for example, to simulate the influence on performance of the routing.
• The transmitter and receiver PICs in the webinar were “flat” (one-level). Can you have hierarchies for design re-use?
Answer: Yes, you can design some PICs as sub-cells first and repeat them many times to build up a complicated circuit. The hierarchies can be preserved in both OptSim Circuit and OptoDesigner.

To learn more about the webinar topics and to schedule a demo, contact our team at pic_support@synopsys.com.

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