Photonic Solutions Enewsletter

February 2018

Synopsys Acquires PhoeniX Software

In February 2018, Synopsys acquired PhoeniX B.V., a global supplier of photonic chip design solutions. With the PhoeniX Software tools, Synopsys is the leading provider of PIC design automation solutions.

Read the press release on our website.

Custom PDK-Based Model Examples

In last month’s e-news, we introduced the S-Matrix/Custom PDK Generation Utility, which creates custom PDK models to augment existing PDKs, create new PDKs, and generate IP. Larger devices can be split into smaller, passive, linear elements for more efficient circuit-level simulation of the entire structure where each element is represented by a custom PDK. In that article, we used a simple ring resonator to demonstrate the simulation procedures and capability of the utility. This time, we will present two case study models.


1. Tunable Cascaded Lattice Filter for Detector Array

Figure 1 illustrates an Si-wire-based lattice filter that was proposed to increase the FSR of a channel dropping filter when compared to a single ring filter for a WDM system. This approach allows the channel bandwidth to be controlled by the number of periods (stages) included. Furthermore, the filter channel position can be tuned by a delay line, the straight waveguide section, connecting the half ring sections. 

Fig. 1: Schematic of Si-wire-based cascaded ring coupler [1]

We use the S-Matrix/Custom PDK Generation Utility to simulate and design one period of the lattice filter cascaded ring coupler, and then use OptSim Circuit to simulate several cascaded periods. The layout of the full structure can be input into Synopsys’ OptoDesigner for mask layout. Figure 2 shows the one unit ring setup in the RSoft CAD Environment. The Si wire in the structure has a 400nm x 200nm cross section. The cladding material is silicon dioxide. The radius of the ring is 2.5 µm and the gap between the ring and straight waveguide is 175nm at the closest point. Five delay line lengths of 0, 50nm, 100nm, 150nm, 200nm, are chosen to form different filter groups.

Fig .2: One unit ring in RSoft CAD [1]

First, the S-Matrix/PDK Generation Utility is used to calculate the spectrum at each port of the one-unit structure shown in Figure 2. The S-Matrix Utility also creates an OptSim Circuit model, a GDSII mask, and a model for PhoeniX OptoDesigner. Figure 3 shows the spectra when launched from Ports 1 & 2, respectively, for one delay line length. Note that these simulations were done using 2.5D (EIM) FDTD.

Fig. 3: The spectra at each port from S-Matrix calculation

Figure 4 shows a schematic in OptSim Circuit using eight periods, each modeled by a custom PDK.



Fig. 4: a) An OptSim Circuit schematic using eight-unit ring coupler PDKs to create a cascaded ring coupler circuit, and b) the OptSim Circuit schematic.

A wideband source launches light to the circuit as shown in Figure 4b. Analyzers at all four ports are used to measure power spectra. The through and drop spectra are shown in Figure 5a, and the results match very well with published results [1]. Figure 5b shows the spectra with several different delay line lengths. 



Fig. 5: (a) Power spectra at the through and drop ports of 8 ring coupler circuit in Fig.4 without delay line; (b) Spectra with different delay line length (nm) 

Next, we build a 4-channel detector array using cascaded designs with different delay line lengths, each tuned to a particular wavelength. The rest of the components in the design are taken from the AIM PDK. The spectra of the six ring coupler are shown in Figure 6. When compared to eight periods, the FSR of six periods is narrower, but it has balanced ER and bandwidth requirements at 1.5 µm to 1.55 µm wavelength range. The number of cascaded periods can be adjusted at the circuit level to optimize trade-off between ER and filter bandwidth. This significantly reduces computational overhead, which would otherwise be required by device-level simulation. 



Fig. 6: (a) Power spectra at the through and drop ports of 6 ring coupler circuit in Fig. 4 without delay line; (b) Spectra of 6 ring coupler with different delay line length (nm)

Figure 7 illustrates this 4-channel detector array with custom and official PDK. 50, 100, 150, 200 nm delay line-length were picked to accommodate center channels of 1504.8, 1519.2, 1533.6, and 1548.0 nm, respectively. The AIM Photonics PDK elements provide input coupling, signal splitting, and photodetection. 

Fig. 7: The schematic setups in OptSim Circuit for 4-channel detector

We put this detector array in an OptSim Circuit schematic and operate it with a 15Gbps NRZ signal. With approximately -11dBm launch power per channel, we obtained very open eye at all four wavelength channels, as shown in Figure 8. 



Fig. 8: (a) Four-channel detector-array PIC in OptSim Circuit; (b) The eye diagram for each channel 

OptSim Circuit provides a netlist to the schematic of Figure 7 to generate corresponding layout in PhoeniX Software OptoDesigner, as shown in Figure 9. It uses the same interface as standard PDK components. 

Fig. 9: Mask in OptoDesigner for the OptSim Circuit photonic integrated circuit (PIC) of Fig. 7 

2. CROW Delay Lines on a Silicon Platform

Slow light is emerging as a promising approach for applications where the dynamic control of the delay is required, such as data synchronization, time multiplexing, and data storage [2]. Coupled-resonator optical waveguides (CROWs) [3] have exhibited advantageous features like on-chip integration, delay tunable, large bandwidth, and transparency to modulation format, and so on. The numerical simulation for CROWs from the device level requires too much simulation resource and is not realistic. It is mainly done with circuit-level tools, such as OptSim, based on analytical or measurement coupling coefficients. Using the S-Matrix utility combined with OptSim Circuit, the design and optimization of CROWs can be realized with a device-level numerical approach.

Figure 10 shows a top view of fabricated CROWs [3]. It consists of eight ring resonators with a radius of 20µm. The silicon waveguide has a 480x220nm^2 cross-section and is buried in a silica cladding. Note that the yellow parts depict the heating wire for modulation (not modeled in this simulation).

Fig. 10: Top View of 8 ring CROW [3]

Figure 11 shows the waveguide-to-ring and ring-to-ring coupling geometries and spectra calculated with the S-Matrix Utility. Due to symmetry, we only need to calculate two input ports for the waveguide-to-ring coupling (Fig. 11a) and only one input port for the ring-to-ring coupling (Fig. 11b).



Fig. 11: (a) Waveguide-to-ring coupling geometry and corresponding spectra for input at Port 1 and Port 2; (b) ring-to-ring coupling geometry and the spectra for input at Port 1

We use OptSim Circuit to build the CROW device as shown in Figure 12. 

Fig. 12: The compound component of 8 ring CROW created in OptSim Circuit

The power spectrum and the group delay plots obtained from OptSim Circuit simulations are shown in Figure 13. In this way, by combing system circuit tool and device tools, we have realized a device-level simulation for a CROW system. The simulation includes the effect of material dispersion, bending waveguide loss, and so on. The custom PDK model approach helps model larger, passive photonic devices as photonic circuits in OptSim Circuit, thereby bringing computational efficiency as compared to rigorous, device level simulations. As an example, the FDTD simulation of one of the rings in the CROW device of Figure 10 took around 16 hours to converge, while the entire PIC of Figure 13 took a few seconds to simulate in OptSim Circuit. 

Fig. 13: The power spectrum and group delays for 8 ring CROWs

For more information, please contact

Download Design Files

  • Download design files from SolvNetPlus (account required)


  1. Koji Yamada, et al., “Silicon-wire-based ultrasmall lattice filters with wide free spectra ranges,” Optics Lett., vol. 28, No. 18, pp. 1663-1664, Sept. 2003.
  2. A. Melloni, F. Morichetti, C. Ferrari, and M. Martinelli, "Continuously tunable 1 byte delay in coupled-resonator optical waveguides," Opt. Lett. 33, 2389-2391 (2008).
  3. A. Canciasmilla, C. Ferrari, “Reconfigurable CROW Delay Lines on a Silicon Platform” Lasers and Electro-Optics 2009 and the European Quantum Electronics Conference.

Visit Synopsys at OFC 2018

Optical Fiber Communication Conference and Exposition (OFC) 2018

March 11-15, 2018
San Diego Convention Center
San Diego, CA
Synopsys Booths #3735 and 1822


Visit Synopsys at booths 3735 and 1822 at the exhibition on March 13-15, where we will showcase RSoft and PhoeniX Software solutions for designing photonic devices, photonic integrated circuits (PICs), and optical communication systems. 

  • RSoft OptSim™ Circuit and PhoeniX Software OptoDesigner provide a complete PIC design flow from ideas to fabrication.
  • RSoft OptSim and ModeSYS™ automate the design of fiber optic systems and multimode optical communications.
  • RSoft component design tools work seamlessly with OptSim Circuit and PhoeniX Software OptoDesigner to provide custom PDK components. In addition, the tools are integrated into Sentaurus TCAD for complete electro-optic device simulation. 

Speak with our staff to learn how you can solve your design challenges with the latest product enhancements and drive the PIC design revolution. For more information about the RSoft products or PhoeniX Software tools, please visit our website.


Join Us for an Evening Reception at OFC

Tuesday, March 13, 2018
5:00 – 7:00 p.m. 

Room 28C, Upper Level, San Diego Convention Center


Synopsys' Optical Solutions Group cordially invites you to an evening reception at OFC. Join us for food and drinks, talk with our software experts, share ideas with other users, and see the latest in the RSoft products and PhoeniX Software tools. 

Please RSVP before March 6 if you plan to attend the reception. We hope to see you there!

Join Us for PIC International Training

April 9-10, 2018
Sheraton Brussels Airport Hotel
Brussels, Belgium


The PIC International Conference team is pleased to announce the launch of PIC International Training. The training event will be organized in partnership with PhoeniX Software and Synopsys.

Synopsys and PhoeniX Software will present a two-day workshop on electro-photonic design automation (EPDA) for photonic integrated circuits (PICs). The workshop is aimed at application and R&D engineers as well as managers interested in understanding the development of PICs and the role of software automation in their design, simulation, and fabrication.

During the first half of the workshop, Synopsys and PhoeniX Software will provide an overview of their software tools and their role in integrated photonics design and manufacturing. Synopsys will describe its photonic tool chain, which features OptSim Circuit for schematic-driven PIC design, as well as the RSoft Photonic Component Design Suite for device design and custom generation of PDK components that can be used in OptSim Circuit and PhoeniX Software OptoDesigner. PhoeniX Software will describe OptoDesigner, a comprehensive tool for PIC design and mask generation that naturally interfaces with OptSim Circuit for full PDK-driven and custom PIC design.

The second half of the workshop will feature live training and hands-on demonstration of the Synopsys and PhoeniX Software tools for PDK-driven PIC design. The top-down training will demonstrate OptSim Circuit for PIC schematic entry and simulation, PhoeniX Software OptoDesigner for PIC layout and mask generation (including its interface with OptSim Circuit), and the RSoft Photonic Component Design Suite for custom PDK development and device design. During the hands-on session, attendees will have the opportunity to work directly with the software under the guidance of technical staff from both companies.