| Industry Insight|
Will You Be 3D-Ready?
3D IC technology promises to deliver compelling business and technological benefits for some market applications. Jamil Kawa and Tom Chau, Synopsys, explain the advantages of 3D ICs that use through-silicon vias (TSVs), and outline some of the design challenges awaiting early adopters.
3D IC is an emerging technology that allows design teams to produce high-density systems consisting of two or more vertically stacked and hermetically sealed dies, which the manufacturer integrates into a single package. Stacking creates a direct metal connection between adjacent dies.
An important feature of “true” 3D ICs is the use of TSVs, which allow designers to connect front-side and back-side metal layers of a die through the substrate. This enables manufacturers to create high-density, higher-performing and lower-power systems.
Figure 1 shows a 2-die stack with both die face down (flip-chip configuration). The red and blue cylindrical objects represent power and ground TSVs through the substrate of the lower chip, while the gray cylindrical objects represent signal TSVs.
Figure 1: Diagrammatic representation of 3D stack with TSVs
Designers today have a number of manufacturing choices, including using a single system-on-chip (SoC) within a package; using multiple dies side-by-side in a multi-chip module (MCM); or using a system-in-package (SiP), which instead of using TSVs, connects multiple chips through traditional package wiring or wire bonding.
3D stacked dies have the potential to enable manufacturers to increase logic density without increasing footprint. Compared to traditional SoCs, the short inter-die paths have less capacitance and inductance and can result in better performance by increasing the bandwidth of inter-chip communication. Reducing the number of connections with high parasitic capacitance through the package and the circuit board can help reduce system power.
3D stacked dies also enable designers to specify the best process technology for each function: for example, using different processes that manufacturers have optimized for memory, logic and mixed-signal. Separating analog functionality (implemented using 130 nm process technology) and digital functionality (built in a 45 nm process) will also improve time to market, enhance reliability and signal integrity of system and save money wasted on extra process steps to accommodate analog voltages in advanced digital process technologies. This approach enables design reuse at a die level – for example, it may be possible to reuse the same 130 nm process analog chip across a number of 3D stacks.
However, 3D ICs have some drawbacks. The ecosystem is relatively immature. There is limited expertise within the design community, the range of design and verification tools is restricted, and few manufacturers have experience of high-volume production. There is an added die manufacturing cost associated with producing TSVs. The higher cost of producing 3D chips may be a barrier to adoption today, but as the technology matures, it will become cheaper and lower packaging costs will offer a significant benefit.
The business benefits that are driving adoption of 3D IC stacks vary according to the target application. Homogeneous stacks can benefit from smaller form factors in 3D. Similarly, stacking memories will enable manufacturers to more or less double integration capacity of dies per package without having to transition to new technology nodes. The first homogeneous memory stacks will appear in production quantities during 2010.
Design teams working on applications such as mobile multimedia require higher performance and less power. Combining heterogeneous dies into 3D stacks has the potential to significantly enhance bandwidth between logic or processors and memory. The industry will begin to see the first production 3D stacks incorporating logic and memory during 2012.
Time to market is another business driver for 3D technology. Analog circuitry is notoriously difficult to design in advanced digital silicon process technologies, so separating it from digital logic could help reduce time to market for complex mixed-signal systems, since this approach opens up the possibility of reusing a complete analog die.
- 3D Challenges
While much of the 3D design process is similar to the traditional 2D flow, there are some specific tool and methodology requirements for 3D implementation. For example:
- Creating a 3D stack involves bringing together dies with different thermal and mechanical properties, which may also result in higher temperatures and thermal flux within the stack. The design team must take steps to properly manage heat sources and dissipation throughout the 3D design flow.
- Integrating a 3D IC design with its package and board is more complex than with traditional SoCs.
- In 3D devices, managing clocks takes on an additional layer of complexity as inter-tier clock skew joins intra-tier clock skew on the designer’s to-do list.
- The test strategy for a 3D IC stack can be a bit more complex when designers use TSVs to connect adjacent dies. The primary issue is that it is impossible to completely test the stack’s inter-tier connectivity until the foundry has assembled it, because each tier is logically and functionally connected to at least one other tier.
- 3D designs need special treatment in the areas of extraction, power rail analysis and thermal analysis. Thermal analysis, especially, is important at all levels of the design flow from pathfinding through floorplanning, placement and verification.
3D stacks offer a number of advantages to chip makers, but there are technical challenges to solve and implementation choices to make. By taking a pragmatic approach, and ensuring that manufacturers match the right 3D stacks to the right applications, the industry will build up the necessary experience to ensure that the development of 3D technology stays on track.
Synopsys is collaborating with several partners across the industry to address the emerging 3D design issues and accelerate the development of 3D stacked IC technologies. Industry collaboration will speed up the development of through-silicon via technologies, help to create robust design flows, and will in turn facilitate the adoption of 3D stacked ICs in the semiconductor industry.
Tom Chau, Sr. CAE Director, is responsible for Synopsys’ power/rail analysis and library characterization products. He has been with Synopsys since 1995. Tom has more than 25 years semiconductor and EDA industry experience and is responsible for strategic customers’ reference flow development with the focus on high performance and low power design and 3D IC initiatives. Tom received a B.S. degree in Electrical Engineering from University of California, Berkeley, and an MBA from San Jose State University.
Jamil Kawa, Group Director of R&D of the Implementation Group of Synopsys, oversees projects in 3-D IC, SIP design and in DFM/DFY. He has been with Synopsys since 1998. Jamil manages the Synopsys Engineering Seminar Series and is also an active member of the technology roadmap committee of Synopsys and of the patent committee.
Jamil received his B.S. degree, EE in 1977 and his M.S. Degree, EE in 1978 from the University of Michigan at Ann Arbor. He also received an MBA in 1988 from the University of Santa Clara.
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