| Technology Update|
High Performance 3D Extraction with Rapid3D
Fast and accurate 3D field solver extraction opens up the possibility of performing post-layout verification in new ways. As Synopsys’ Shekhar Kapoor, senior marketing manager, explains, high accuracy 3D extraction runs that used to take days or hours, now take only hours or minutes with Rapid3D technology.
Do mainstream designers really need 3D extraction accuracy? Most design teams believe that it’s only relevant for characterization of library cells or validation of the chip-level extraction tools. That certainly used to be the case, but design needs are rapidly changing.
Designers are integrating a lot more sensitive custom circuitry in their latest SoCs, including custom analog, high-speed digital, memory and full-custom IP. The result is that successful SoC design is becoming highly dependent on how these disparate analog and digital circuits function. Design teams need to spend disproportionately more time verifying these circuits at the post-layout level compared to the past. Today, SoCs also depend on complex, sensitive clock trees, and it’s important to accurately design, extract and verify these in order to meet the overall design specification.
As well as design issues, there are process issues too. The latest technologies bring new parasitic effects to the fore due to increased process variation. As process node geometries decrease, sensitivity of the circuits to parasitics also increases.
These design and process effects change the way that design teams approach the verification of their designs. They want to extract and analyze larger blocks with increasing accuracy, but cannot afford the runtimes traditionally associated with high-accuracy extraction.
StarRC Custom Unified Solution
Last year Synopsys introduced StarRC™ Custom, which combined Synopsys’ two gold standard extraction technologies in a unified solution: full-chip high-perfomance ScanBand™ (pattern-matching) extraction and Raphael™ NXT 3D field solver extraction.
Rapid3D technology builds on, and replaces, the gold-standard Raphael NXT engine as our new field solver extraction technology. It is embedded inside StarRC Custom and aims to deliver a number of key benefits to designers who want to use 3D extraction for mainstream designs. It:
- delivers very high performance and capacity,
- enables design teams to get the best from their multicore compute environments, and
- allows users to define exactly how accurate the extraction will be, all the way to “gold standard” attofarad (10-18) accuracy. Performance is dependent on the accuracy bounds that the user specifies.
- Advanced Algorithms
Re-writing Rapid3D from the ground up has allowed us to take advantage of the latest software techniques and algorithms to boost performance and capacity. Rapid3D uses an advanced random walk algorithm, which compared to other techniques, enables us to provide:
- more flexibility to choose between high accuracy and performance,
- improved handling of design size and complexity, and
- more efficient use of computer memory,
- while taking advantage of parallelism for better multicore support.
The random walk method is a production proven technique for extracting layout parasitic capacitances. Leading foundries and design companies have been using it for highly accurate extraction for over a decade. The advanced random walk algorithms incorporated inside Rapid3D enable designers to accurately compute post-layout capacitance with fewer and faster iterations. This means that SoC designers can extract net capacitances in a large block – or the entire chip – in a matter of minutes or hours.
Ultra High Performance and Capacity
Benchmarking Rapid3D against traditional random walk field solvers on over 50 customer designs ranging from 28 nm to 65 nm process technologies yields interesting results (Figures 1 and 2).
Figure 1: Faster extraction with Rapid3D
Figure 2: Rapid3D reduces memory requirements
We have seen performance increases across all designs – up to 100X in some cases. In terms of memory efficiency, Rapid3D uses about 6X less memory than our previous solution Raphael NXT, which itself uses memory very efficiently. This allows design teams to take advantage of even their low-memory machines (e.g. 2GB per core) for running extraction. Superior capacity is one of the key advantages of Rapid3D technology over other field solver-based solutions.
Highly Linear Multicore Scalability
Re-architecting Rapid3D technology enables design teams to maximize the use of the hardware in their design environments by distributing jobs within the same machines (multi-threading) and across different machines (multi-processing).
Design teams can use both approaches together to enable the optimal use of their resources in a memory-constrained environment, and at the same time maximize throughput.
Rapid3D’s multicore technology provides a built-in, automated fault tolerance capability that allows the processing to proceed without interruption should a core become unavailable by transferring its job to another available core. It also incorporates smart load balancing that makes use of waiting cores ‘on the fly’. This ensures that Rapid3D fully utilizes each core and doesn’t have to wait for cores to finish processing their own data.
Flexible Silicon-accurate Solution
Rapid3D delivers gold standard accuracy. We benchmarked Rapid3D for accuracy on over 20,000 test structures with varying pitch across various process nodes from 28 nm to 130 nm. The results (Figure 3) show a 1% correlation with silicon.
Figure 3: Rapid3D correlates to within 1% of silicon
Rapid3D allows designers to easily trade off accuracy and performance – a distinct advantage of the technology versus some other commercial 3D field solver solutions. Being able to customize the extraction to the specific accuracy requirements of the circuit can provide an order of magnitude speedup in performance. It also eliminates the risk of over- or under-design by enabling designers to select a level of accuracy appropriate to the circuit. This “What You Set Is What You Get” flexibility allows users to set any accuracy goal and then have the tool extract parasitics that are consistent with that goal. For example, a typical gate-level extraction job might require an accuracy level of 5%, while the characterization of standard cells or critical analog circuits might require an accuracy level of 1%. A key benefit provided by Rapid3D is that its use of memory is independent of the accuracy settings: that is, Rapid3D maintains its high capacity even with accuracy and performance trade-offs.
Creating input data for field solver extraction can be very time-consuming, especially for large designs. Rapid3D can take advantage of the process modeling technology and standard interfaces within StarRC Custom to accelerate the extraction flow. Rapid3D’s compatibility with StarRC’s widely qualified Interconnect Technology Format (ITF) ensures broad support through multiple generations of process technologies.
Figure 4: Rapid3D integration with StarRC Custom delivers proven reliability, modeling, and ease of use
Designers can do all net 3D extraction with Rapid3D or supply a list of critical nets that require its 3D extraction accuracy while extracting the non-critical nets with the StarRC Custom ScanBand technology. StarRC Custom partitions the polygons in the design, applies Rapid3D technology on a subset of the design and produces a single netlist for all nets, delivering results on user-specified nets with field-solver accuracy. The design team can then load the netlist into a simulation environment for circuit analysis. This flexibility of combining full-chip capacity with field-solver accuracy provides a complete spectrum of extraction technologies within a single extraction flow to help designers become more productive.
Rapid3D’s integration with StarRC Custom allows designers to perform high-accuracy extraction for multiple custom implementation and analysis applications, such as characterization with Liberty™ NCX, custom layout with Galaxy® Custom Designer, simulation with CustomSim™, and signal integrity signoff with NanoTime.
Rapid3D technology is the ideal solution for a number of applications.
Library and IP development: Rapid3D’s fast runtime and low memory usage enables efficient full cell and library characterization. Design teams can characterize a standard cell library with over 400 cells overnight.
Custom AMS circuits: Rapid3D delivers sub-femtofarad resolution required for AMS designs, such as analog-to-digital converters (ADCs) and differential amplifiers, which are highly sensitive to layout parasitics.
Memory array designs: Rapid3D provides silicon-accurate extraction of critical bit lines and word lines to enable accurate analysis of read and write access times. Rapid3D enables designers to produce consistent results to match the capacitance of word and bit lines across cells.
Ultra-high-performance gate-level and transistor-level digital designs: Rapid3D, because of its high performance and capacity, allows detailed analysis of high-speed blocks and datapaths, and critical nets such as clock networks.
Today’s SoC designs demand greater accuracy, which means field solver extraction technology must be able to deliver the performance and capacity required for full-chip analysis.
Rapid3D technology, part of Synopsys’ StarRC Custom advanced parasitic extraction solution, offers up to 20 times speedup in performance compared to traditional field solvers running on a single core. It also offers ultra-low memory usage and attofarad accuracy.
On multicore platforms, Rapid3D’s performance improves almost linearly with the number of cores. It is highly scalable, and offers up to 54 times performance boost on 64 cores, which provides the performance and capacity necessary to perform full-chip extraction
The integration of Rapid3D in StarRC Custom gives designers an easy-to-use embedded 3D extraction solution, which, because of its faster turnaround time, extends its use to new design scenarios.
Shekhar Kapoor is senior product marketing manager for parasitic extraction signoff products at Synopsys. He has 15 years of experience in semiconductor and EDA industries in design engineering and marketing positions. He holds an MS in Electrical and Computer Engineering from Virginia Tech and an MBA from Haas School of Business, University of California, Berkeley.
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