Innovative Ideas for Predictable Success
      Issue 3, 2009


Technology Update Technology Update
In-Design Physical Verification Delivers Timing-Aware, Signoff-Quality Fill For Faster Time to Tapeout
David Pemberton-Smith, corporate applications engineer in the Implementation Group, Synopsys, explores the benefits of generating metal fill as an integral part of the design process.

The Need for In-Design Physical Verification
With increasing design complexity and size, more design rules and mounting DFM challenges, design groups face exploding turnaround time (TAT) for physical verification through the design flow. At 45nm and below, it is routine for designers to spend 2-4 weeks during design and 4-6 weeks for final signoff to ensure that the design will comply with the foundry-specified DRC and DFM requirements. Designers spend most of that time iterating between point tools, using a physical verification tool to flag errors with signoff validation and a place-and-route (P&R) tool to implement the fixes in a timing-aware environment.

Metal fill is a prime example of this phenomenon. Engineers who fail to implement signoff-quality metal fill during place and route may find themselves iterating between the point tools to achieve DRC and timing closure.

Todayís Signoff Metal Fill Challenges
Most place-and-route tools have some capability of generating fill. Although they may have algorithms that come close to generating the correct density, they are not intended to guarantee signoff. For signoff, the foundries rely on physical verification tools since they are built on efficient polygon engines that work well hierarchically to produce correct data quickly. This leaves the designer with two possibilities:

  • Use the place-and-route tool to generate a first pass fill, check and complement that with fill from a physical verification tool, stream in the design back into a P&R tool to check timing. Iterate between the P&R and physical verification tool until there are no timing or fill violations.
  • Let the physical verification tool generate the fill and compensate for the timing effects by leaving extra timing margin in the design.

Figure 1 shows how time consuming and cumbersome it is to switch from a place-and-route tool to a separate, non-interfacing physical verification tool to generate fill. After completing place and route of a design, the engineer needs to verify that the design passes DRC. It will be necessary to go back and forth between tools every time an ECO is required.

Figure 1: Typical place and route to physical verification flow

It is difficult to minimize the timing impact of metal fill and at the same time pass DRC when using different data representations between a place-and-route tool and a physical verification tool. Consider the following case study of fill generated for a 5.3mm2 design at 45nm having 1.6 million cells and generating a 2.1GB GDSII file. Before generating fill, the design had a worst negative slack of 70ps and a total negative slack of 25ns. The team found density violations on metal layers 4, 5 and 6.

The following summarizes the results of each iteration of fill generation for a timing path group:
  1. On the first attempt, the team gave all metals 2x the minimum spacing for critical nets. The team removed all density violations, but the worst negative slack and the total negative slack worsened.
  2. On the second attempt, the team specified a spacing of 0.4m. In this case, the two slack values worsened and there were density violations on metal layers 4 and 5.
  3. On the third iteration, the team set all spacing to critical nets on metal layers 1, 2, 3 and 6 at 1μm, and the spacing for metal layers 4 and 5 at 2x the minimum spacing. This time, the team eliminated all density violations, but both the worst negative slack and the total negative slack worsened
  4. Finally, the team specified a large spacing to critical nets: 1μm. This spacing improved and timing did not deteriorate. Density violations for metal layers 4 and 5 along the boundary of the block remained, but these are acceptable since the team will place the block in question in the top block and correct density by the placement of neighboring blocks.

This case study shows that it takes many iterations to close timing and generate fill to meet all density requirements. Each iteration required approximately 6.5 hours (1 hour for fill generation, two 2.5-hour runs for timing analysis and 20 minutes for the density check). Adding this time for all the iterations totals approximately 26 hours of processing.

Integrating Metal Fill within the Design Process
To reduce the time it takes to do metal fill, it is necessary to find a solution that allows users to produce DRC-correct fill while checking for timing impact within an integrated tool environment. Consider the integrated metal fill flow shown in Figure 2. Layout engineers would generate all fill within the place-and-route tool, allowing them to verify timing and run DRC. It would no longer be necessary to stream in and out many times between separate tools, thus eliminating some time-consuming iterations. In addition, it would be possible to reduce iterations further if the fill generated were timing-aware. If the tool creating the fill polygons is aware of critical net information, it can automatically avoid adverse effects on the timing of the design.

Figure 2: Integrated metal fill flow

Thus the requirements of an integrated fill solution are:
  • Fill needs to be generated within the native place-and-route environment using recognizable data structures
  • Fill generated within the place-and-route environment must be DRC-clean by construction
  • Ability to generate fill that minimizes the impact on timing
  • Easy solution to use, set up and learn
  • It should be possible to incrementally modify fill in response to ECOs to reduce turnaround time and schedule impact
  • Users must be able to view the generated fill within the place-and-route tool

An In-Design Metal Fill Flow with IC Validator and IC Compiler
To solve the complexities associated with using two point tools to create fill, Synopsys has introduced its new physical verification tool, IC Validator, which is architected to seamlessly integrate with IC Compiler, its flagship place-and-route solution. This solution allows users to create signoff quality fill that is DRC-clean, verify the timing impact of that fill, avoid creating fill near critical nets, and eliminate unnecessary streaming in/out while remaining within the native Milkyway database environment. Figure 3 shows how IC Validatorís fill generation and DRC checking capabilities integrate into IC Compiler. Once layout engineers have routed a design and successfully run DRC, they specify an IC Validator fill runset using a simple set_physical_signoff_options form. Next, they launch fill generation from the signoff_metal_fill form, which invokes the foundry-provided runset. The fill generated will be DRC-clean by construction since the signoff fill runset is provided by the foundries. They place the resulting fill hierarchically to minimize disk space usage of the resulting design, and save it into IC Compilerís Milkyway™ database. Now that the design contains fill, the layout engineer can do timing analysis. If a post-route ECO is required, it is possible to regenerate fills for all layers or only those metal layers that were part of the ECO, using the same IC Validator runset.

Figure 3: In-design metal fill flow in IC Compiler

User Benefits of In-Design Fill Flow
Designers can save a lot of time using the IC Compiler/IC Validator metal fill flow. When regenerating the block level or chip level fill, the runtime is 10x faster compared to P&R fill. In addition, the ability to generate fill incrementally for a specified window or layer saves considerable time compared to full fill generation. The time savings demonstrated above add up dramatically over the life of a project. Consider, for example, the metal fill process for designs having respectively 1.7 million, 5.4 million and 17.8 million instances. For each design, the layout team performed four 100μm x 100μm area ECOs and three individual layer ECOs. Each design will benefit from time savings by:

  • avoiding streaming in and out of tools since the fill is generated directly into the Milkyway database,
  • running only area-based ECOs instead of running the full area. In addition, you also save stream out time, and
  • running only layer-based ECOs instead of running all layers.

By remaining within the Milkyway database, for each of the seven ECOs, the layout engineers saved the costly stream in/out time. For the largest design, they saved close to 30 hours from not streaming in/out. The bigger the design, the more time the engineer will save.

Table 1 shows the total savings for each design, which is calculated by adding the stream in/out savings, the area-based ECO savings and the layer-based ECO savings. These add up to a considerable amount of time. The layout engineers saved almost 50 hours for the 17.8 million instances design.

Table 1: Total time savings

The IC Compiler/IC Validator In-Design Signoff metal fill feature provides a seamless solution for creating, viewing and modifying fill without having to leave the IC Compiler environment. Because this solution is P&R based and uses foundry signoff metal fill runsets, the resulting fill is both signoff-quality and timing-aware. The flow is not only easy to set up and use, it also supports layer- and area-based ECO flows. In addition, hierarchical representation of fill minimizes disk space usage.

David Pemberton-Smith is corporate applications engineer within the Implementation Group of Synopsys.

©2010 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.

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