Innovative Ideas for Predictable Success
      Issue 3, 2009


Industry Insight Industry Insight
Collaborating for System-on-Chip Design Success at 32/28nm
To design a chip at 32/28nm and below, companies have to bring together the right silicon technology, IP, tools and methodology. Ana Hunter, foundry vice president of Samsung Semiconductor Inc, and John Chilton, senior vice president of marketing and strategic development at Synopsys Inc., explain how the collaboration between ARM® the Common Platform™ alliance and Synopsys, delivers a proven solution for all design teams tackling projects at this process node.

ARM, Synopsys, and the Common Platform alliance – consisting of Chartered Semiconductor Manufacturing Ltd, IBM and Samsung Electronics Co., Ltd – have signed an agreement to combine low-power processor architecture, integrated design flow, and system-level IP on the Common Platform alliance foundry process. Their objective is to deliver a vertically optimized solution for 32/28nm mobile systems on chips (SoC) designs that all design teams can access – not just the select few with control over their own proprietary processes.

The primary objectives of this collaboration are to reduce risk, design cost and improve time to market for advanced mobile products by taking advantage of developments in material science, processor architecture and physical IP, mobile multimedia implementation and SoC design.

By combining the specific expertise of each company and allowing earlier access to each other’s technology, the collaboration will help bring the technology to market more quickly and reduce risks for those adopting it.

Market and Technology Drivers
Over the last 20 years, the chip design industry has seen massive changes in areas of technology, competitive pressures and design complexities. Table 1 highlights some of these key developments.

Table 1: New market competitive pressures

Companies are experiencing increased barriers to entry created by massive costs resulting from technology approaching physical limits. Up-front costs are rising and shorter product life cycles reduce the part volume available to amortize these costs. Increasingly complex designs drive design time up, but the penalties for being late to market are becoming more severe. This chaos in the value chain is what is driving new interdependence models for both economics and technology development, and is the primary driver behind the creation of the ARM - Common Platform - Synopsys technology collaboration.

Forming the Multi-Way Collaboration
Although the collaboration was formally announced at the recent DAC conference, the work actually started more than a year ago enabling the demonstration of silicon success and early tool enablement in the Common Platform ‘Innovation-Optimized’ DAC exhibit .

The Ultimate Design Node
The 32/28nm high-k metal-gate (HKMG) technology process offers designers the best of everything and boasts key attributes with respect to 32nm Poly SiON process that include:

  • Power: up to 100 times reduction in gate leakage
  • Complexity: approximately 5% lower complexity
  • Scalability: approximately 40% better Vt mismatch – and therefore better Vmin
  • Manufacturability: gate first enables cost-effective poly resistor
  • Reliability: proven technology for lifetime requirement

Project Skills and Expertise
These days, it takes a broad range of skills to create a design in advanced process technologies. They include system-level skills, circuit design, knowledge and expertise in manufacturing technology and design infrastructure (Table 2).

Table 2: Examples of project expertise

The collaboration between ARM, the Common Platform and Synopsys alliance brings together the companies’ respective expertise In accordance with the agreement, all parties have aligned their strategies, technology roadmaps and customer delivery schedules to collectively solve the challenges surrounding the creation of designs on Common Platform HKMG 32/28nm process, and achieve their aims of early enablement and integration of their SoC designs on the process.

Collaboration Contributions
Each company brings unique technology and expertise to the collaboration that, when combined through collaboration, creates an optimized solution not available elsewhere. By collaborating, we provide faster time to market with reduced risk and lower costs for customers. Figure 1 provides an overview of how each organization will contribute to the collaboration to achieve the overall objective.

Figure 1: Contributions to the Collaboration

ARM brings a robust portfolio of logic, memory and interface IP. Furthermore, ARM will integrate its widely adopted ARM Cortex™ processor family with their full suite of libraries optimized for low power and high performance applications. Working together, ARM and Synopsys will further optimize ARM’s physical IP with the Synopsys design flow to deliver low power and system cost benefits when targeting the Common Platform alliance 32/28nm process.

Common Platform alliance
The Common Platform alliance 32/28nm process uses an innovative HKMG approach to address the limitations of polysilicon technology. It leverages the research and development efforts of the International Semiconductor Development Alliance (ISDA) to offer a high-performance, low-power manufacturing platform. Furthermore, the process offering is available with synchronized foundry services from Chartered, IBM and Samsung, ensuring that customers have freedom of choice and maximum sourcing flexibility.

Synopsys provides a comprehensive suite of tools and components from its Galaxy™ Implementation Platform, Lynx Design System and DesignWare® connectivity IP. Synopsys is focused on reducing design complexity, achieving performance and power goals, and speeding up the technology’s time to market.

By tuning the automated Synopsys front-to-back flow to achieve maximum benefit with the Common Platform technology with ARM processor and physical IP, the collaboration is aiming to deliver a streamlined implementation path that can reduce the total cost of developing an optimized SoC, while helping speed up time to market and reduce risk.

The work in the collaboration began over a year ago, and demonstrated early results of our join 32nm low- power tool and IP enablement at the 2009 DAC event.

The collaboration has proven 32nm low-power silicon technology and methodology via delivery of multiple testchips, including the world’s first 32nm ARM Cortex processor, and Synopsys USB 2.0 nano PHY.

Figure 2: Testchips from ARM and Synopsys

As well as producing testchips, the collaboration has delivered early 32/28nm low-power tool enablement, having qualified HSPICE®/CustomSim (HSIM®), StarRC™, IC Validator, DC Graphical and IC Compiler with the process technology and ARM physical IP.

32nm Connectivity IP
To design at any process node, designers need access to a broad range of silicon-proven connectivity IP. Synopsys and the Common Platform alliance have worked together to validate the latest Synopsys DesignWare USB 2.0 PHY. The USB 2.0 PHY passed NTS’ compliance certification tests for the 32nm Common Platform process (Figure 3).

The silicon results from the test-chip provided feedback on process performance, providing additional confirmation of design rules, Process Design Kits (PDKs) and device characteristics at 32nm, as well as the tools and flow used in the development process.

Figure 3. Synopsys USB 2.0 NTS test summary certificate

ARM Testchips
Since the first ARM test structures taped out in July 2008, ARM has produced four further testchips and has more in development. The silicon results have helped the collaboration to refine the design rules and update PDKs, quantify power, performance and area results, and demonstrate the use of cells and IP in an embedded CPU application.

32/28nm HKMG Milestones
The collaboration and silicon process technology have achieved a number of key milestones, including:

  • January 2007: Innovative high-k metal-gate (HKMG) technology announced
  • December 2007: 32nm gate-first, HKMG technology announced, including functional 32nm bulk and SOI SRAM (<0.15µm2)
  • April 2008: 32nm Common Platform alliance design evaluation kit released and performance/power advantages validated
  • July 2008: 32nm Common Platform alliance Design Alpha Level Kit released
  • September 2008: ARM, the Common Platform alliance collaborate to enable energy-efficient 32/28nm systems on chip
  • February 2009: ARM features 32nm silicon implementation of mobile processor
  • March 2009: 28nm Common Platform technology Design Evaluation Kit released for general access and performance/power advantages validated
  • July 2009: Synopsys receives notification from National Technical Systems that its implementation of the 32LP USB had been High-Speed compliance certified.
  • July 2009: ARM, the Common Platform alliance and Synopsys publicly announce at DAC the collaboration to deliver vertically optimized solution for 32/28nm mobile SoC designs
  • Sept 2009: Common Platform alliance qualifies Synopsys IC Validator for 32nm design rules checking

Current Collaboration Activities
At present ARM, the Common Platform alliance and Synopsys are working together on advanced modeling and design methodologies, including a 32/28 LP production flow based on the Lynx Design System which incorporates pre-validated IP and an optimized design flow (Figure 4).

Figure 4. 32/28nm Low-Power Optimized Production Design System

Over the coming months, the collaboration will continue to expand the amount of physical and processor IP, connectivity IP, PDKs and tools available, and will make announcements regarding further development of the 32/28nm HKMG design platform.

The collaboration will be presenting more technical details, results and proof points at the ARM’ TechCon3 event taking place at the Santa Clara Convention Center, California, on October 21-23.

©2010 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.

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- Executive video
- Common Platform alliance
- Synopsys: Innovation Optimized

“No single company can do this on their own; no single company can leverage expertise from across the entire design chain like this all the way from silicon to application software.”
Warren East
ARM chief executive officer
“Designing a 32/28nm chip is very difficult, as many things can go wrong. In the past, many people would pull together their IP, silicon technology, the tools, and methodology; however, a single failure would cause the whole flow to fail.”
Dr. Aart de Geus
Synopsys chairman and chief executive officer