| Industry Insight|
The Next Era of Rapid Prototyping
Hardware-assisted verification means "big box emulation", or does it? Juergen Jaeger, Director of Product Marketing for the Synplicity Business Group, Synopsys, talks about the evolution of hardware assisted verification and outlines the improvements Synopsys has made to its Confirma Rapid Prototyping platform.
The last 15 years or so have seen various hardware-assisted tools and technologies help engineers to verify chip designs. Using dedicated hardware instead of general purpose computers was one of the first ways that design teams accelerated simulation in the verification process. Another approach is in-circuit emulation, which lets designers map the whole ASIC into a dedicated emulation box and then connect it to outside stimuli.
Using hardware technologies to assist with chip verification is more relevant today than it has ever been. Chips are getting bigger and more complex, and simulation runs are getting longer, but hardware-assisted verification is helping designers to control those simulation runs. But even more importantly, as the software content in new chip designs increases, a major system validation challenge emerges: verifying the software in the hardware context. The only way to do this in a manageable timeframe is to deploy a rapid prototyping system that is fast enough for a software developer to run a meaningful number of instructions, such as booting up the device's operating system.
The Rapid Prototyping Advantage
Internally, big-box emulators use either custom ASICs or an array of custom processors. This dedicated and proprietary architecture allows designers to quickly map the design under test to the emulator. Big-box emulators also support very large designs 100 million ASIC gates and more. However, while emulation speed is faster than software simulation, for many of today's designs it's often not fast enough. The other main drawback of big-box emulators is that they are very expensive. The demands of their physical size and power mean that they usually need an air-conditioned environment where they can be connected as a network resource for the whole verification team to use.
The disadvantages of big-box emulation have led companies to build their own FPGA-based hardware prototypes to suit the needs of their design projects. FPGA prototyping systems have several advantages over big-box emulation. They run much faster (Figure 1), they are more affordable, they are deployable, and many copies can be made available to the software design team. For the same investment in one big-box emulator, a company could probably buy 40 or 50 rapid prototyping systems. The comparisons are similar to those between investing in a mainframe computer and a desktop computing environment.
Figure 1. Relative performance for a range of verification technologies
In the past, many companies chose to build their own FPGA prototype systems often called FPGA boards, emulation boards or build your own' boards. But for a number of reasons, building these boards in-house has become more painful and economically less attractive.
Why Use Commercial Boards?
Increasingly companies are turning to commercially supported FPGA-based rapid prototyping systems. The advances made in FPGA technology, although a blessing for prototyping purposes, make board design more complex. High-capacity FPGAs have high pin counts and having multiple FPGAs on one board is challenging. Add to this issues such as signal integrity, power distribution, component density and temperature profile, and it becomes obvious that it take time and expertise to solve these challenges.
In addition, it is becoming more difficult to map an ASIC design onto a prototyping board, especially if it's a 20- or 30-million gate design. A design of this complexity needs multiple FPGAs, which in turn require more sophisticated partitioning and implementation tools in order to transfer the ASIC design to the FPGA(s).
Another reason why building boards in-house is becoming less popular is that prototyping systems need to have sophisticated debugging features. There is little point in producing a fast prototyping board that helps the design team to discover an error very quickly, only for it to take a long time to figure out why the error occurred in the first place. Ideally, the prototyping environment must allow the designer to perform root cause analysis quickly and easily.
In the past, some customers who have built their own prototyping systems will have designed the main printed circuit boards themselves, sourced FPGAs from one vendor, bought their design tools from yet another supplier, probably developed some home-grown software, and then assembled the whole system in-house. This is quite an undertaking for many chip companies on top of the chip design itself, and it has become even more of a burden as the chips they are designing have become more complex.
For an increasing number of design teams, a commercially supported, robust, rapid prototyping platform offers compelling advantages over the in-house development route.
Confirma Rapid Prototyping Platform
Confirma, Synopsys' rapid prototyping platform, consists of a variety of hardware and software components. It includes the main motherboards that host the FPGAs, as well as a choice of over 60 extension boards that allow designers to connect the system to a variety of outside world inputs and outputs. This allows developers to quickly configure their systems to accomplish tasks such as taking in video data or connecting the system to an Ethernet network.
Confirma includes the software components that address the implementation of the design into the prototype as well as the debug aspects, allowing designers to perform root cause analysis when they discover a bug.
As well as providing a robust, commercially supported rapid prototyping platform that enables traditional hardware-assisted verification tasks, the Confirma platform introduces new technologies that allow designers to take advantage of rapid prototyping across more of the system validation flow than ever before.
The CHIPit® automated prototyping systems feature a patented methodology with programmable interconnects instead of hardwired ones. That is, the connections between the multiple FPGAs are no longer fixed wires, but they are programmable under software control. This technology supports a smoother and more automated implementation flow. Designers can make changes to the system configuration more easily and reliably using software, instead of having to physically change the prototyping setup.
With CHIPit, designers can now benefit from cycle-accurate co-simulation by connecting Synopsys' VCS high-performance simulator directly to the prototyping system. For even higher-performance system modelling it also provides a SCE-MI compliant transaction-level interface between the prototyping system and a software model running on the workstation.
It is also possible to link the hardware prototype to Synopsys' virtual platform, Innovator. This gives designers a hybrid prototyping system where some of the models reside inside Innovator and other models are implemented in real hardware within the prototyping system.
Full Visibility Debug
In the past, it has been difficult to debug with FPGA-based prototyping systems. In order to see what was going on in the prototyping system it was necessary to define which signals had to be monitored before the system was built, so that those signals could be routed out to pins on the FPGA or be probed with a software logic analyzer. This approach limits the number of pins that can be used, but an even greater problem is the need to know ahead of time which signals might be needed to properly debug the system.
Within Confirma, Identify® Pro debug software, which uses technology called TotalRecall, provides 100% visibility into the design under test. Moreover, Identify Pro uses the existing VCS® simulator as the debug frontend and visualisation tool, thus combined the best of both worlds excellent debug analysis features in VCS and the unparalleled performance of a rapid prototyping system.
With this technology, the process of debugging the prototype becomes far more natural and far more productive. The prototype system can run freely until an error occurs. At that point the designer creates a test case and loads it into VCS and performs a root-cause analysis while the prototype continues to run. For the first time, a prototyping system now has the same level of debug analysis as a software simulator.
FPGA Tool Flow for ASIC Designs
In order to verify an ASIC design within an FPGA-based prototyping environment, the ASIC description needs to be conditioned so that it is suitable for mapping to single or multiple FPGAs.
Synopsys' Certify® multi-FPGA implementation and partitioning software allows designers to take designs that have been coded for ASIC implementation and map them to an FPGA architecture. Certify takes advantage of special FPGA features and components. For example, Certify converts gated clocks for FPGA implementation, maps ASIC memories into FPGA memories and also automatically maps more complex blocks, such as DesignWare® components, into equivalent FPGA functions.
Certify also partitions the design to fit multiple FPGAs, which often necessitates pin multiplexing multiple signals share one pin to overcome the lack of sufficient pin numbers when connecting the FPGAs together.
Figure 2. Confirma is part of Synopsys' comprehensive verification solution
Rapid prototyping systems are a powerful, pre-silicon development platform allowing designers to develop software and to validate hardware-software interfaces. FPGA prototypes have sufficient performance to run a meaningful number of software instructions for example, to bring up the operating system or validate the device with real data. Prototyping systems are affordable, opening up the possibility of deploying localized compute power throughout entire software teams.
The Confirma platform is part of Synopsys' complete software-to-silicon verification flow. It transforms prototyping from an ad hoc assembly approach to a mainstream, properly supported system validation and verification solution.
The new capabilities in Confirma provide features on developers' desktops that were previously only available in expensive big-box emulation systems. These capabilities include the addition of transaction-level interfaces, programmable interconnects, and support for cycle accurate co-simulation to connect to software simulators so that designers can reuse testbenches as part of the prototyping environment.
Juergen Jaeger is Director of Product Marketing for the Synplicity Business Group, Synopsys.
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