| Industry Insight|
IC Design: Rethink Recover
In his keynote speech to the San Jose Synopsys User Group, Dr. Aart de Geus, Synopsys chairman and CEO, considered the impact of the global economic downturn on todayís technology markets. In part one of a two-part article, Synopsys Insight reports the highlights from the speech.
The recession has the semiconductor industry in a bind: many chip companies are keeping their inventories low because itís hard to predict where their next orders will come from. To make matters worse, long manufacturing lead times make it difficult to respond quickly to new orders when they come.
The current downturn is similar in scale to the 2001 downturn, which was by far the biggest in semiconductor history (Figure 1).
Figure 1. Semiconductor peak-to-trough cycles
Most semiconductor experts think chip sales will stabilize and probably plateau somewhere between 30 and 35 percent down from its September 2008 level. Itís much harder to predict how long it will take for sales to recover, but itís clear that the current recession will have a major impact on the future of the whole industry.
Financial recessions tend to accelerate changes in industry. One current trend is that of chip companies moving to a fabless (or fab-lite) business model, or teaming up in a consortium such as the IBM common platform consortium. This has come about as a result of chips becoming increasingly complex: few companies have the financial resources to manufacture them. It now costs up to $3.5bn to build a 300mm state-of-the-art fabrication plant and up to $1.5bn to develop a new technology node.
Another key industry trend is the growth of systemic complexity. More and more companies are augmenting their core products with additional features and capabilities. The iPhone, for example, is more than just an electronic product: itís the conjunction of electronics, applications, service providers and media downloads. The failure of just one of these things can cause the entire value chain to fall down. Thatís one of the key challenges in an economy that right now is looking at who the winners and the losers will be. Businesses want to try to tie themselves to the value chains that will survive.
The recession is forcing design teams to focus on profitable design. Figure 2 shows the tapeout trends for advanced designs, virtually all of which Synopsys is able to tabulate.
Figure 2. Advanced design tapeout trends
In the past, new process nodes have ramped up like clockwork. Figure 2 shows that 40/45nm process design starts have already started to level out, while some design teams are competing to get to the latest 28/32nm process nodes for their most advanced designs.
It is apparent that design teams are still targeting the older nodes: there are potential cost benefits for those that can use well-proven, existing technology. However, getting the last cent out of each chip using 90nm and 130nm requires some very advanced design.
The trend evident in Figure 2 is a result of it being much more difficult to design chips profitably at the latest technology nodes. Managing millions of transistors on a chip is hard enough, but designers must also consider how power, timing, verification and manufacturing yield Ė issues that once could be addressed independently Ė are now interrelated and affect each other. In solving one problem, they have to ensure they donít create another elsewhere.
To address this complexity and all its consequences, design teams are investing heavily in resources (Figure 3). As a result non-recurring engineering (NRE) costs are growing rapidly, especially for the early part of the design debugging, which involves verification and synthesis. Embedded software development is also a major and growing cost component.
Figure 3. Contributions to chip NRE
Excessive NRE investment hinders profitable chip development: if the NRE price goes way up, so too must the market value. For example, to support a development cost of $90m for a 32nm design, the vendor has to be able to find at least a $400m market for that chip. There are not that many markets where this is possible. Therefore a primary industry objective has to be to bring development cost down.
The fact that chips are becoming more complex doesnít necessarily mean that the cost of their development has to grow uncontrollably. For example, the industry has been quite successful in using automation and applying design discipline to control the cost of physical design, as Figure 3 shows. To ensure there is a return on investment in chip design, the EDA industry must continue to rein in the cost of design, so that $100m design costs donít become the norm. To meet this objective the industry must focus precisely on those areas that will rise uncontrollably if it simply continues to do what it is doing today.
While cost is one key issue, schedule is the other. There is nothing new here: those that are late to market will lose a lot. The vendor that enters the market first sets the pricing, and the second one comes in later at a lower price. Typically the third entrant is prepared to compete on cost alone. For the first entrant, itís very important to control the time aspect of the design flow.
- When looking at project schedule, designers must consider the entire design Ė both hardware and software. Software is a growing part of the value of SoCs because designers can use it to:
- create chip derivatives without incurring hardware re-design costs;
- manage risk: manufacturers can provide software upgrades to fix problems even after they have shipped the product, and
- extend product lifecycles by introducing new applications that add value to the product.
Itís not surprising, then, that semiconductor companies are now hiring similar numbers of software and hardware engineers. Designers have to work together to integrate hardware and software, and most importantly, verify it together or in parallel.
Verification is getting out of hand: adding more transistors adds to verification complexity, as does growing integration between digital, analog, and embedded software. Engineers need faster, higher throughput and more thorough verification to satisfy the demands of growing hardware and software complexity.
There is no question that the recession will accelerate a number of trends; the question is how the industry deals with them. A crisis should never go unused. It is an opportunity to put incremental changes to one side and think fundamentally about how to change things for the better, to rethink everything for recovery readiness.
The next installment of Dr. de Geusí keynote will review the new Synopsys products, services and technology that are addressing the key issues of total cost of design and schedule.
Aart de Geus
Since co-founding Synopsys in 1986, Dr. Aart de Geus has expanded Synopsys from a start-up synthesis enterprise to a world leader in electronic design automation (EDA). As a technology visionary, he is frequently asked to speak on topics related to the electronics industry. As one of the leading experts on logic simulation and logic synthesis, Dr. de Geus was made a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in January 1999. He was also honored for pioneering the commercial logic synthesis market by being named the third recipient ever to receive the IEEE Circuits and Systems Society Industrial Pioneer Award. In 2002, shortly after transacting the largest merger in EDA history, Dr. de Geus was named CEO of the Year by Electronic Business magazine; and in 2004, Entrepreneur of the Year in IT for Northern California by Ernst & Young. In November 2005, Electronic Business magazine chose Dr. de Geus as one of "The 10 Most Influential Executives." Dr. de Geus is active in the business community as a member of the board of the Silicon Valley Leadership Group (SVLG), TechNet, the Fabless Semiconductor Association (FSA), and as Chairman of the Electronic Design Automation Consortium (EDAC). He is also heavily involved in education for the next generation, having created in 1999 the Synopsys Outreach Foundation, which promotes project-based science and math learning throughout Silicon Valley.
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