Innovative Ideas for Predictable Success
      Volume 3, Issue 4


Technology Update Partner Solution
Advanced DFT Implementation
Manu Baby and Vijay Sarathi, both designers at Dubai Circuit Design, outline their use of a Synopsys implementation flow that incorporates advanced DFT techniques.

Achieving acceptable levels of reliability for modern SOCs makes testability increasingly important. Nowadays, test implementation is a key challenge because of the need to effectively target low cost, high coverage patterns that are time-aware, power-aware and placement-aware. So a well-defined test flow with relevant test features is essential to attain complete testability with quick turnaround time.

Figure 1. Advanced DFT Requirements

Changing Test Requirements
The complexity of process technologies has grown tremendously over the years. Each new technology node introduces smaller geometries and new process steps. As a result we now have to address defect mechanisms that we could previously ignore. Scan compression, Small Delay Defect (SDD) test, power-aware test and multi-voltage test are some of the new test techniques that have attracted considerable attention. Our test flow incorporates the complete Synopsys test tool suite within the Synopsys Pilot design environment. We used the flow to implement advanced DFT on a recent SoC design. It included advanced techniques such as multi-voltage DFT synthesis, use of an on-chip clock (OCC) controller and timing- and power-aware ATPG.

Chip Specification
Table 1 shows the main features of our design – a data encryption/decryption engine.

Technology TSMC 65 nm low power 7LM4X2Z
Die size 3.45 x 3.45 mm2
Total gate count ~ 4.8 million with 148K sequential cells
Design speed 333 MHz max with 4 primary clocks
No of macros 70 memories and 1 PLL
No of MVDD blocks 2
No of IO pads 67
Package type Wire bond
Core voltages 1.2 V & 0.96 V
Table 1. Design specification and features

The key test features include:
  • MBIST using serial interface
  • Scan compression synthesis
  • On-chip clock controller for at-speed
  • Multi-voltage DFT considerations
  • IO PAD Test with 1149.1 JTAG
  • ATPG – stuck at, transition SDD, bridge and IDDQ

Implementation Flow
Figure 2 shows the overall DFT implementation flow for our design. It comprises three main stages – DFT implementation, pattern generation and pattern verification. The flow uses Synopsys DesignWare® (DW) / Test components: On-Chip Clocking Controller, DW BSR Cells, Tap Controller, DW RAM BIST and Compressor/Decompressor logic all implemented within the Pilot design environment.

The Pilot design environment supports the overall DFT flow that incorporates the latest test features. The built-in methodologies, flows and scripts served as an excellent start point for our DFT requirements. We could take advantage of the reference multi-voltage DFT flow within Pilot for implementing our design. We also made use of other advanced test support including MBIST integration, adaptive scan implementation, on-chip clock (OCC) controller integration and small delay defect ATPG.

The well-defined tool flow and database structures within Pilot helped us to experiment with and implement the latest test features in a very short time. We could modify the default scripts to suit our needs.

Figure 2. DFT implementation flow

Overall DFT Area Overhead
Table 2 gives a detailed account of the area overhead due to the different test components in the design. The DFT DW components amount to just 39.4K gates, which in the context of the entire chip area is almost insignificant.

The scan sequential elements contribute most to the area overhead. Using TSMC LP 65 nm technology, adding scan to each sequential element requires approximately three additional gates. In other words, the overall DFT area overhead depends largely on the number of sequential cells in the design. The total test area overhead is 13%.

Module TSMC 65nm LP area μm2 Gate count
DFT support 66 45.833
DW RAM BIST 49702 34515.056
BSR cells 2690 1868.04
TAP logic 564 391.66
On chip controller 375 260.415
Compressor 1190 826.383
Decompressor 2161 1500.684
Total test DW component area 56748 39408
Scan flops area overhead(147K) 628389 436378.45
DFT logic total 685137 475786.538
Functional logic total ( With Scan Flops) 5818534 4040622.751
Pure functional logic 5190145 3604244.294
Area overhead 13% 13%
Table 2. DFT area overheads

The following sections outline the key steps in our test methodology.

Memory BIST
Our design only uses around 70 memories, which amounts to about 40K bytes that we had to test. All of the memory macros are RAMs. The DW RAM BIST meets this requirement precisely. It comes with the basic memory testing features with the standard algorithms and is a cost-effective memory test solution.

We used Synopsys Core Consultant to implement and integrate DW RAM BIST with the design memory macros. 1149.1 JTAG interfaces with the memory controller to allow us to configure and observe the MBIST mode register.

Table 3 summarizes the MBIST configuration.

No memories Total size BIST area Algorithms Test time
at speed
Test time
at speed
70 40K bytes 378K gates March LR,
March C0,
1.11mS Passed
Table 3. MBIST configuration

The DW RAM BIST supports a choice of algorithms. It also supports enable-configurations for memory selection that can potentially take care of all power and test time-related concerns. The pipeline option of DW RAM BIST is an added advantage to achieve quick and easy timing closure provided the memory interfaces are registered. Features in BSD Compiler made it easy for us to integrate the top-level memory test serial interface.

Multi-voltage DFT Synthesis
The ASIC is a multi-voltage design with three different power domains. Some of these power domains are switchable and some operate at a reduced voltage compared to the rest of the chip.

DFT synthesis for a multi-voltage design starts with setting the appropriate scan configuration, as shown in Figure 3. By default, DFT Compiler recognizes the voltage/power domains and clusters the scan chains within the respective domains. The ‘set_scan_configuration’ command has ‘power_domain_mixing’ and ‘voltage_mixing’ switches that can be set to true or false to enable or disable power domain/voltage mixing while stitching the chains. In order to minimize the number of level shifters in the design it is better to disable voltage/power domain mixing.

The latest versions of the Synopsys tools support the industry standard UPF (Unified Power Format) to define the power intent of the design.

Figure 3. Multi-voltage DFT synthesis flow

OCC Integration for At-speed Test
Performance and signal integrity issues demand an accurate and cost-effective at-speed manufacturing test to achieve high-quality silicon. We used the Synopsys On Chip Clocking (OCC) controller to generate the at-speed pulses for at-speed test.

DFT Compiler easily integrates the on-chip clocking controller for at-speed testing and helps the designer do away with any manual modification to the Standard Protocol File (SPF) for the launch and capture at-speed ATPG requirements.

Placement-aware Scan Chain Re-ordering
IC Compiler, Synopsys’ place-and-route product, supports placement-aware scan chain repartitioning and reordering. The flow is to perform scan synthesis in Design Compiler®/DC-T using DFT Compiler and then reorder the chains in IC Compiler during placement and clock optimization. The advantages of physically-aware scan chain reordering include wire length reduction, congestion minimization, DFT area impact reduction and reduced switching power. The reordering also takes into account the different voltage/power domains and multi-voltage specific cells that exist in a low power multi-voltage design.

Using IC Compiler we reduced the scan chain wire length (sub-block level) from 893,125 μm to 364,158 μm with no degradation in the timing. We also minimized the number of clock buffers crossing in the scan chain up to 70% with less congestion.

Scan Compression
We used Synopsys’ DFT MAX Compression to implement scan compression for TATR (test application time reduction) and TDVR (test data volume reduction). During the course of this implementation, it became apparent that DFT MAX Compression is one of the simplest and easiest solutions to deploy.

Test data volume, tester time budget and congestion are the three important factors that we consider while arriving at the optimal compression ratio for a design. It is always better to do some experiments with different compression ratios before deciding on one. Increasing compression beyond a certain limit only improves TATR and TADR marginally, while incurring bigger congestion penalties.

To find the optimum compression ratio, we experimented with different ratios to figure out the point of diminishing returns with respect to TATR and TDVR. Fixing this point as the upper limit, we picked the highest compression ratio that kept design congestion within acceptable limits.

It is always advantageous to use compression because it reduces the test pattern volume and test time. For very big and complex designs, designers should implement modular scan compression to alleviate top-level congestion.

Small Delay Defect and Power-aware ATPG
Shrinking geometries need new fault models that can capture new defect types. Small delay defect and power-aware ATPG have received considerable attention in the test industry as we move towards processes below 90 nm.

TetraMAX® ATPG for small delay defect test extends the basic transition fault model to target small delay faults through the longest timing paths. It uses timing information generated by PrimeTime® static timing analysis to guide the ATPG process, using slack-based ATPG to target small delay faults and standard transition delay ATPG to target the longer-delay faults. No design or DFT implementation changes are required to enable SDD test. Parameters in the tool allowed us to make tradeoffs between pattern count and delay effectiveness (a measure of the small delay defect coverage).

Excessive power consumption during scan testing is a major concern since it can impact delay-sensitive at-speed tests in devices that are otherwise good. Implementing sub-block level ATPG, providing multiple scan enables, restricting multi-clock capture and qualifying clock gates with scan-enable are some of the common practices to reduce peak power during scan test.

But the power-aware test capability in TetraMAX ATPG provides a more automated approach to reducing both peak power and average power during scan testing. For shift mode, TetraMAX ATPG generates power-aware patterns by controlling the fill data of non-care bits (don’t-care scan cells) to save power. The concept is to reduce the number of cells that switch during the shift operation. For capture mode, TetraMAX ATPG limits power by observing a designer-specified switching budget for every pattern it generates.

The overall power analysis is performed using Primetime PX and WaveView Analyzer to sign off the ATPG patterns.

Table 4 below describes the overall ATPG statistics of our design. Our fault graded test pattern set includes stuck at, bridge, IDDQ and transition small delay defect patterns.

Fault type Scan
Test time
at 10MHz
Stuck at
745 696 99.04% 4148160 0.051 S Passed
Stuck at
22328 327 99.67% 1540565016 0.730 S Passed
745 4189 95.93% 24966440 0.312 S Passed
22328 1113 98.37% 198808512 2.49 S Passed
745 24 96.49% 143040 N/A Strobes
with SDD
745 8928 95.90% 53210880 0.66 S Passed
745 9 49.21% 53640 0.6 mS Passed
Number of external chains = 8
Number of internal chains = 211

Table 4. Overall ATPG Statistics

DFT Verification
We performed direct pattern validation for all ATPG and JTAG vectors for the quality assurance of the test vectors. We ran functional simulation to test the correctness of the MBIST operation. We ensured timing and power closure for all test modes in the various timing corners.

We validated all test patterns (ATPG/ JTAG/ MBIST) using Synopsys’ VCS® simulator and signed off all test modes for timing and power using PrimeTime SI / PrimeTime PX.

Our test solution using the Synopsys test tools and Synopsys Pilot flow provides an effective path to high-quality manufacturing test with rapid turnaround time. When moving from 90 nm to 65 nm geometries, we highly recommend using adaptive scan to deal with the test time because of the large set of patterns required to accommodate stuck-at, delay, bridge and other tests. The flow enables SDD testing to catch the increasing number of small delay defects.

High complexity with shrinking technologies and process variation calls for high-quality test tools with more fault models to cope with new types of defects. In the future, we must pay more attention to crosstalk-aware ATPG to detect crosstalk defects which are a combination of bridge and timing-aware defects – using a kinetic/dynamic bridge fault model now available in the latest release of TetraMAX ATPG (2008.09).

About Dubai Circuit Design
Dubai Circuit Design (DCD) is the leading force in chip design innovation in the Middle East mainly focusing on the 65 nm and below technology nodes. DCD’s current focus is to provide complete RTL to GDSII design services to the fabless chip design companies in the US, UK and Europe. DCD’s mission is to provide its world-wide customers with predictable chip design services and to create a collaborative environment for its skilled engineers, which fosters creativity and innovation while empowering them with its established state-of-the-art computing infrastructure.

Manu Baby
Manu Baby is a Senior Design Engineer focusing mainly on DFT activities in Dubai Circuit Design, Dubai Silicon Oasis. He has more than 9 years of experience in VLSI design specifically involved in the Test, Synthesis, RTL and STA for various domains such as wireless communication, graphics and networking complex SOCs. He is also a co-author for two technical papers related to DFT. Prior to Dubai Circuit Design, he was working with Wipro Technologies as a DFT and Test Consultant. Manu holds a bachelors degree in Electronics Engineering from Cochin University of Science and Technology, India.

Vijay Sarathi
Vijay Sarathi is a Senior Design Engineer with Dubai Circuit Design, Dubai Silicon Oasis. He has more than 6 years of experience in IC design with specific focus on logic design (RTL), synthesis and static timing analysis. Prior to joining DCD, he worked as a design engineer on multiple ASIC projects with Texas Instruments, Bangalore. Vijay holds a BE in Electronics and Communication Engineering from National Institute of Technology, Trichy, India.

©2008 Synopsys. Synopsys, Inc, the Synopsys logo, Design Compiler, PrimeTime, Star-RCXT, TetraMAX and VCS are registered trademarks or trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.

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"Excessive power consumption during scan testing is a major concern since it can impact delay-sensitive at-speed tests in devices that are otherwise good."