| Industry Insight|
Progress in Products, Chips and Design
In his keynote speech to the San Jose Synopsys User Group audience, Dr. Aart de Geus, Synopsys chairman and CEO, reviewed the amazing progress in products and chip design made over the last 10 years. In part one of a two-part article, Synopsys Insight reports the highlights from Dr. de Geus' speech.
In the last 10 years the industry has made tremendous progress, and nothing illustrates this more than the latest wave of hot new consumer products.
Take GPS products, for example. Innovative designs like the Dash Express Navigation System (Figure 1) have taken the functionality of GPS to a new level by providing internet-connected navigation. Using two-way live connectivity, Dash delivers real-time and relevant information to the car, but also creates a GPS community, so people can help each other to avoid traffic problems and share information about their destinations.
Figure 1. Dash Express navigation system
In the area of home entertainment, the Moxi Multiroom HD digital media recorder (DMR) (Figure 2) can stream HD video into TVs throughout the home – a major step towards a fully connected video home. Video technology is essential in driving the semiconductor industry forwards. Video pixel count is going to define technology that is used for data capture, transportation, storage, data manipulation and display. What’s more, the amount of video data that systems must manage is expected to grow massively in years to come.
Figure 2. Moxi Multiroom HD DMR
The Samsung F700 (Figure 3) is the first phone to compete with the iPhone in OS and user interface capabilities, and includes smart touch screen technology with vibration feedback. It incorporates ‘always on’ connectivity, and despite having a 2.78 inch 440 x 2240 pixel touch screen its power consumption is extremely low.
Figure 3. Samsung F700
Apple is known for its innovative products, but its contribution to making electronics ‘cool’ is also extremely important to the industry. Apple’s latest MacBook Air (Figure 4) incorporates a trackpad that recognizes multi-touch gestures, and it’s just 0.76 inches thick. Very cool…
Figure 4. Apple MacBook Air
All of these products represent amazing progress in chip design – by Synopsys customers in the case of the examples quoted above. Taking just three specific chip design examples, it is possible to begin to quantify the progress made over just 10 years, and better understand the implications for the future of design.
The Chip Inside
The progress in microprocessor design has been truly phenomenal. In 10 years the clock speed has increased by 10x while the number of transistors has increased by 100x (Table 1). The move to architectures based on multiple cores has helped to limit dynamic power dissipation, a trend that accompanies a significant increase in the number and the amount of on-chip memory. The shift to multi-core devices that depart from the traditional von Neumann architecture will have a fundamental effect on the software world and the way that developers produce software.
Driven by the changing needs of the processors, the microprocessor design process has evolved from a custom-based, largely manual flow, to an automated, high-level hierarchical design flow.
Table 1. Progress in microprocessor design
|Microprocessors||Intel® Pentium® II Processor||Quad-Core Intel® Xeon® Processor|
|CPU clock||233 MHz – 300 MHz||2.83 GHz|
|Number of transistors||7,500,000||820,000,000|
|Process||0.35 µm||45 nm|
|FSB||66 MHz||1333 MHz|
Cellular chip products have also become dramatically more sophisticated. In 1998, the Qualcomm Q Phone was state of the art and even then the processing power was impressive, with around 20 MIPS performance and storage consisting of 8MB ROM and 2MB RAM. 10 years later the HTC Touch Dual delivers 740 MIPS and includes embedded storage consisting of 1GB Flash, 128MB ROM and 64MB RAM. Today’s wireless data rates of around 7Mbps are able to support video transmission.
Continuing the video theme, the growth in clock frequencies and transistor counts for graphics processor devices have brought them to a point where they are rapidly approaching the capability to support full reality rendering (Table 2).
Table 2. Evolution in graphics processor design
|Graphics processors||Riva 128 NV3||NVIDIA GeForce 9600|
|Core clock||100 MHz||650 MHz|
|Number of transistors||3,500,000||505,000,000|
|Process||0.35 µm||65 nm|
Progress in chip design across all of these products has benefited from significant changes in design styles over the years. 10 years ago designs typically consisted of a few blocks with a large ‘sea of cells’. Today, design styles are significantly different. Chips now consist of many different regions and blocks that include multiple cores, voltage areas and memories. The issues that designers are concerned with have also changed. As well as performance and area, design teams must now manage complexity and power, be able to accurately predict the project schedule and control cost and reliability.
Figure 5. Typical Design Style 1998
Figure 6. Typical Design Style 2008
Progress in Design Automation
Of course, design environments must keep up with the needs of evolving chip complexities and design styles, and all Synopsys product areas have advanced dramatically over the last 10 years.
With synthesis, around 10 years ago Synopsys’ focus was predominantly area and timing. Since then Synopsys has improved support for test and low power optimization, introduced topographical technology to enable accurate prediction of post-layout timing, power and area without wireload models, and automated synthesis for multi-voltage design. The latest enhancements in Design Compiler® Graphical help RTL designers to avoid wire routing congestion problems before they occur.
In 1998 Synopsys did not offer its own place and route tools. 10 years on Synopsys has a portfolio of layout tools that can manage hierarchical as well as flat design styles, and include features such as sign-off driven timing closure, advanced timing optimization, automated die-size minimization, multi-corner, multi-mode optimization and most recently native floor planning.
Chip verification has been one of the most pressing issues for design teams over the past decade. Starting from a strong position in Verilog and VHDL simulation Synopsys has made substantial progress with added support for SystemVerilog and SystemC, implemented coverage, assertions and testbenches in native technology, enhanced debug and visualization, defined and implemented the Verification Methodology Manual and significantly enhanced Synopsys’ portfolio of verification IP. Most recently, enhancements to Synopsys’ verification products boost support for low power verification.
Like verification, low power design is one of the key focal areas for today’s design teams. 10 years ago tools were able to reduce switching activity and capacitances to help limit dynamic power consumption. Since then, the control of leakage power has added to the challenges that design teams must confront. Leakage current emerged as a major issue with the transition from 130nm to 90nm technologies. From a design perspective, leakage current has added a level of complexity to design that is currently more challenging to solve than any other technical issue. Power affects timing, signal integrity, manufacturability and many other design parameters.
Synopsys tools now support many advanced low power techniques such as multi-voltage design and verification. With IP being such an important part of many designs, much of the Synopsys DesignWare® IP has been optimized for low power. The Low Power Methodology Manual, written by Synopsys and ARM, is a comprehensive and practical guide to managing power in system-on-chip designs. During 2007, UPF became the industry standard for low power.
The advances in products, chips and technology are a good indication of the progress made as an industry, but none of this progress happens without people.
Synopsys now runs eight user groups around the world, and SNUG San Jose itself has grown from around 500 attendees in 1998 to over 2,200 today. Customer input to user groups sets the technology agenda. This starts with the people who take on the responsibility of becoming technical chairs, right through to every person who attends and provides valuable feedback to give Synopsys user groups the reputation they now have as being the best EDA conferences in the industry.
In 1998 the user group agenda centered on the hot topics of the day, which were synthesis and makefiles, functional verification, test and FPGA design. Today’s user group hot topics include low power, design at advanced geometries, verification methodology and design productivity. The last topic in that list – design productivity – is an issue that has risen in prominence and considering the interaction between technology and economics it’s easy to see why.
SNUG is a great barometer for design trends and it’s interesting to see Moore’s Law in action through the eyes of Synopsys users. Figure 7 shows the adoption of new process technology nodes over time according to data collected from SNUG audiences.
Figure 7. Adoption of new process nodes
Clearly the industry continues to move to smaller geometries. What is evident is that the number and spread of different technology nodes in use today is greater than ever. In other words, designers are extending the lifetime of older (cheaper) process technologies. If a design team is able to achieve the chip’s required performance and area by continuing to manufacture using an older process node there is the potential for considerable cost savings and improved profitability.
The industry’s obsession with cost reduction is down to the huge number of products that have ‘gone consumer’ and the new markets for these products. Estimates suggest that another 500 million consumers will bolster demand for consumer electronics in the next 10 years, most of these new consumers originating from China and India. A focus on cost is essential to compete in these new markets where disposable income levels are far below those in more established markets.
Cost control is evident in many forms. Some companies choose to manufacture certain lines using old geometries while others race forward to manufacture using the latest, smallest geometries to achieve the same outcome – the lowest cost. Companies are cutting unprofitable products and choosing to invest in areas where they lead the market. The economics of developing new semiconductor processes and chip manufacturing are two key issues that semiconductor companies must consider. Many have concluded that it makes sense to outsource manufacturing and focus on differentiating through chip design, while the specialist foundries take care of process development and manufacturing. Looking at the numbers, it’s easy to see why…
The Economics of Advanced Geometries
Figure 7 shows a consistent two-year interval between production ramps for the latest technologies, and presently the industry is at the beginning of the 45nm adoption curve.
It costs about $1bn to develop a new process node and then a further $3bn to build a state-of-the-art fabrication plant. While the cost per device has steadily come down, the cost of developing new technology nodes may soon exceed the ability to get a return on that investment. The economics of running a fabrication plant only add up when the chip manufacturing volumes are extremely high, which is why more and more traditional chip manufacturers are choosing to partner with foundries rather than go it alone.
The renewed focus on cost explains the attention now given to productivity. In relation to chip design, productivity is not a word that was used that often 10 years ago. Feedback from the SNUG community states that unpredictable schedules and challenges is the top ranked reason (55 percent) which directly impacts productivity.
Power management is clearly the top design challenge according to 49 percent of the SNUG community. The rise of leakage power has challenged Moore’s law, and many of the possible design solutions require knowledge of the physical effects occurring within the chip.
Increasing design size and complexity is an issue for over 40 percent of the SNUG community who are designing chips over 5M gates. Multiple issues arise with increasing design complexity, not least the increased runtime and memory required to enable design tasks to be completed.
EDA is at the intersection of design where many problems can only be solved by the tools having knowledge of the new physics of advanced process technologies ‘from below’, and at the same time understanding the increased system level functionality ‘from above’. With each new technology node, EDA environments will need to understand more about the physics and more about the system capabilities.
Part 2 of Dr. de Geus' keynote will review the new Synopsys products, services and technology that are addressing the key issues of power management, performance and productivity.
Aart de Geus
Since co-founding Synopsys in 1986, Dr. Aart de Geus has expanded Synopsys from a start-up synthesis enterprise to a world leader in electronic design automation (EDA). As a technology visionary, he is frequently asked to speak on topics related to the electronics industry. As one of the leading experts on logic simulation and logic synthesis, Dr. de Geus was made a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in January 1999. He was also honored for pioneering the commercial logic synthesis market by being named the third recipient ever to receive the IEEE Circuits and Systems Society Industrial Pioneer Award. In 2002, shortly after transacting the largest merger in EDA history, Dr. de Geus was named CEO of the Year by Electronic Business magazine; and in 2004, Entrepreneur of the Year in IT for Northern California by Ernst & Young. In November 2005, Electronic Business magazine chose Dr. de Geus as one of "The 10 Most Influential Executives." Dr. de Geus is active in the business community as a member of the board of the Silicon Valley Leadership Group (SVLG), TechNet, the Fabless Semiconductor Association (FSA), and as Chairman of the Electronic Design Automation Consortium (EDAC). He is also heavily involved in education for the next generation, having created in 1999 the Synopsys Outreach Foundation, which promotes project-based science and math learning throughout Silicon Valley.
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