| Industry Insight|
Solutions for Leakage Power Optimization
A 65nm chip can lose as much as 60 percent of its power to sub-threshold leakage. Power dissipation due to leakage current is an endemic problem that the industry must address if it is to continue to satisfy demand for feature-rich battery-operated consumer electronics. John Stabenow, Director Marketing, Analog and Mixed Signal Business Unit, Synopsys, explains the issues, evaluates the merits of a number of solutions and proposes a compelling alternative - an automated methodology based on Synopsys' library layout tool Cadabra® that achieves significant sub-threshold leakage power reduction.
The IC industry is in a state of revolt; transistors are refusing to turn off. It's an uprising that's been making headlines with its demands for more power since its inception, around the 180nm technology node. Despite having a common goal, however, this is a fractured, disorganised revolution with many causes, and by identifying and addressing them, a peaceful solution is anticipated.
There is a serious point behind this melodramatic introduction; while the general increase in static power has been labelled with the umbrella term sub-threshold current leakage', there are numerous causes for increased static current at 90nm and below. As shown in Figure 1, they go beyond sub-threshold leakage, to include effects such as gate oxide tunnelling leakage, junction leakage, hot carrier injection leakage, gate induced drain leakage and punch-through leakage currents.
Figure 1. Sources of leakage. In 90nm and 65nm technologies, subthreshold leakage current dominates.
Sub-threshold Leakage Dominates
It was at the 180nm technology node that sub-threshold leakage first became a significant issue. At 90nm, gate leakage also became apparent and as migration to smaller nodes continues, the effect of others shown will begin to emerge.
But having identified the numerous contributors to leakage current, it is still felt that sub-threshold leakage will remain the dominant concern through to 65nm technologies; it is here that the immediate concerns are grounded and, therefore, where mitigation efforts are being directed.
The leakage, more technically known as weak inversion conduction, hasn't so much been introduced as exacerbated by smaller geometries, being inherent in transistor operation. While it can actually be useful in analogue operation, it is particularly problematic in digital designs, where the vast majority of transistors are deployed. As more design flows move into 90nm and 65nm technologies, this increase in static power goes beyond inconvenient; it could actually begin to dictate performance envelopes, which will have a far reaching impact.
For instance, if battery life continues to be negatively affected due to power issues, the popularity of next generation portable devices may come under pressure, while as form factors continue to shrink, dissipating the heat generated by leakage will also become a real problem.
As the research above implies, the causes of increased leakage have been known for some time and, subsequently, their consequences anticipated. To combat them, a number of techniques are now emerging from the research labs, such as supply voltage optimization, reverse body biasing, and multiple threshold voltage assignment and state assignment. It has also been found that the associated aspects of smaller physical dimensions, including temperature, voltage and process corners, all influence sub-threshold leakage.
Because it is so endemic, various solutions have been proposed to tackle the problem. At a high level, techniques such as gating or removing power from whole areas of a circuit when it's not in use have been demonstrated, while at the substrate level, optimizing individual transistors can yield results if the right balance between acceptable leakage and performance degradation is struck.
Both of these solutions have merit, but with a large legacy in design cell libraries introducing alternative and wide-reaching circuit design techniques may not be as simple as it sounds. And with digital designs now comprising multi-billion transistors, manually optimizing individual transistors isn't really an option either. The approach put forward by Synopsys is to tackle the problem by applying an optimization flow, that interjects between these two extremes; by targeting the ASIC cell libraries used to create the designs and optimizing them at the transistor level for lower power operation.
Adjusting Transistor Channel Lengths
Of the solutions outlined above, adjusting transistor channel dimensions can provide in the region of a 30 percent reduction in leakage current, with acceptable increases in dynamic power. Adjusting channel lengths has been found to be effective at these nodes because, somewhat simplistically, leakage current is highly influenced by channel length in transistors with smaller channels.
However, adjusting channel lengths isn't without its consequences; other parameters may suffer. As with any three dimensional object, a transistor's channel has width, length and height; each of which may be increased or decreased individually. This gives a large degree of movement and each of these dimensions has a measurable influence on the cell's area and relative delay, as well as the transistor's operation.
For instance, it is known that a channel length increase will not only lower the leakage current (Ioff) but also raise the threshold voltage (Vth), which leads to a further reduction in Ioff. However, with every technology node reduction, supply voltage and, consequently, Vth, comes down and it is this reduction that leads to faster transistor switching. Increasing Vth, therefore, will have the effect of increasing not decreasing switching time and as a result, the cell's overall delay could be degraded.
It's a dichotomy; the solution to reducing leakage in digital circuits is to make them slower, but market forces will not tolerate slower digital circuits.
Unfortunately, because of this, the answer isn't to modify all transistors in a cell library uniformly, even though that may have the desired effect of reducing overall leakage. In order to preserve the library's many favourable features without introducing unwanted artefacts, a more considered approach is needed.
To give an example of how those features are preserved; analysis may show that in addition to adjusting the channel length, the width may also need to be increased, as this will maintain the same input to output cell delay.
Automating this process requires an EDA tool flow with an appreciation for the effects channel width/length increases will have, to the transistor and in relation to switching and parasitic delay, as well as noise margins and allowable area increases.
The design flow proposed by Synopsys to achieve this comprises a number of commercially available tools, including: a SPICE simulator; a standard cell library characterization tool; a circuit optimizer; a library layout generation and migration tool, and a parasitic extraction tool.
Figure 2 shows the effects on an optimized NAND2x2 cell, following a new layout had been generated using Synopsys' library layout tool, Cadabra. In brief, a 10 percent increase in channel length resulted in a 34 percent reduction in sub-threshold leakage and no increase in overall cell area. Applying the proposed flow to an established, commercial 90nm library has also shown a significant reduction in sub-threshold leakage and power.
Figure 2. Results of optimizing a NAND 2x2 cell for leakage
With the consumer electronics market remaining a prime driver for the semiconductor industry, the threat that increased static power could have on new product development and end product sales has focused attention on this growing issue. But through the efforts of EDA vendors and the introduction of innovative design flows such as the one described here, the challenge of sub-threshold leakage can be met head-on.
John Stabenow is Director of Marketing in the Analog and Mixed Signal group at Synopsys, and has more than 18 years experience in design, EDA sales and marketing. At Synopsys, he has been involved with the full-custom physical design software development teams, including the Cadabra Library Development team.
John holds an MBA and BS in Applied Economics, both from the University of San Francisco.
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