Discovery Verification Seminars – India and Israel
Synopsys’ successful verification seminar program continues with a series of events in India and Israel. The seminars include presentations and demonstrations to bring chip designers and verification engineers up to date with the latest tools and techniques.
Verification remains one of the most challenging issues for all engineers. Its complexity quadruples each time gate count doubles, and design teams consistently point to undiscovered functional errors as the primary cause of chip respins.
The Synopsys verification seminars are an opportunity for designers and verification engineers to bring their knowledge of the latest verification tools and methodologies up to date, and understand how others are using advanced verification strategies to improve productivity and design quality.
The seminar agenda is designed so that a full day of seminars provides a wealth of useful information for any verification engineer or designer. A general morning session includes a complete overview of the Synopsys Discovery System-to-Silicon Verification solution, a special focus on solving system-level verification issues and a keynote address on real customer challenges in verification today. This is followed by a choice of verification tracks in the afternoon, exploring specific verification solutions in detail. These tracks cover:
- Verification methodology (based on the widely adopted Verification Methodology Manual - VMM)
- Verification for designers
- Analog and mixed-signal verification
Space will be limited in each location and demand for these free seminars is expected to be high, so early registration is strongly recommended.
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