Profile of a SNUG San Jose Designer
Networking with fellow chip design professionals is a major part of the worldwide Synopsys Users Group (SNUG) meetings. If you are thinking about attending the 2007 SNUG San Jose event—April 2-4 at the Santa Clara Convention Center in Silicon Valley, California, you might like to know what sort of designers you will meet there. Here with the answers is Synopsys Insight’s profile of the ‘typical’ SNUG San Jose designer…
More than 1500 of the most talented design engineers in the global electronics industry are expected to attend this year’s SNUG San Jose, making it the largest gathering of EDA tool users in the world. SNUG is both a top technical conference and an unparalleled opportunity for attendees to discuss common challenges and explore solutions to real world design problems. SNUG’s program is largely driven by the users themselves. This year’s San Jose program will feature more than 70 technical sessions presented by both Users and Synopsys experts and will cover the full spectrum of Synopsys solutions from concept to silicon.
But exactly who from the design community attends SNUG San Jose? Based on survey data, our snapshot profile of the typical SNUG San Jose designer draws interesting comparisons with overall averages gathered from the worldwide 2006 SNUG and miniDAC tour, which covered 13 locations across North America, Europe, Japan and Asia.
In terms of job function and company, your fellow attendee is most likely a design engineer working for a fabless chip company. Like his global colleagues, he is almost certainly working on standard cell-based SoC design.
In terms of design complexity and frequency, it is fair to say that high-speed digital design will be a core competence for the typical SNUG San Jose designer, with more than a third of attendees in 2006 working on designs with clock speeds in excess of 500MHz. As is the case with his global counterparts, the SNUG San Jose designer is currently working on a design targeting 90nm, although a transition to 65nm is highly likely for his next project.
Figure 1. High Speed Design (MHz) Evident at SNUG San Jose
A SNUG San Jose attendee selected at random is most likely working on a communications project, which is also the most popular chip design category for Synopsys users on a global basis. However, the design is more likely to be for a wired communications application while wireless design is more common globally. Given the similarities in applications profile, the target manufacturing production volumes for the SNUG San Jose attendee are broadly in line with the worldwide data.
Table 1. Summary Profile of the SNUG San Jose Attendee
Design Flow Choices
As a route to chip implementation, the SNUG San Jose attendee is likely to perform the backend design as an in-house activity, following a customer-owned tooling (COT) design flow. The majority of global designers also prefer a COT route, although the main alternative, which is to hand off the design to the ASIC vendor, is a more popular option with the global design community.
In common with the global designer, the SNUG San Jose attendee is likely to cite functional (logic) problems as the main reason for chip respins.
The likelihood of the SNUG San Jose design engineer using SystemVerilog as a design language as part of an integrated verification strategy is greater than it is worldwide. Also, adoption of SystemVerilog Assertions (SVA) is more advanced among SNUG San Jose designers. In line with both of these trends, the SNUG San Jose designer is also interested in the use of SystemVerilog for testbench implementation and is more likely to be using formal property checking as part of a portfolio of verification technologies.
Intellectual Property Trends
The global profile shows an increasing preference to deploy third-party IP within a design: the average number of IP blocks is on the rise in all regions. The SNUG San Jose attendee broadly matches this trend. However, while USB is the most popular IP on a global basis, an attendee of SNUG San Jose is just as likely to have experience integrating PCI Express IP into his design.
Yield is a growing concern for the SNUG San Jose designer. With the majority of designers in attendance likely to be taking measures within the design to enhance manufacturing yield, SNUG San Jose is once again ahead of the global averages. In line with this trend, average yield goals are also rising with a range of design and manufacturing techniques employed to reach those goals.
Although this profile characterizes the interests of the typical attendee, in reality the SNUG audience is both broad and diverse. For example, the number of designers that declared their current process geometry as 250nm or greater is comparable with the number that identified 45nm as their target technology. While almost a third of attendees are working on design projects of 5 million gates or more, more than a third are working on chips of much less than a million gates. CAD and verification engineers/managers attend in similar numbers, and the range of applications is diverse, encompassing not only the strong communications theme, but also computers, peripherals and consumer devices. Alongside mainstream digital design, there is a growing interest in analog and mixed-signal and custom design issues within the SNUG San Jose audience.
Whatever your technology specialization, SNUG San Jose is a forum where you will find people with an overriding common interest: sharing information and best practices to find creative solutions to common design challenges.
The Synopsys team looks forward to welcoming you there.
SNUG San Jose will be held April 2-4 at the Santa Clara, California Convention Center.
Find program details and register at: http://www.snug-universal.org/northamerica/na_sanjose.htm
For more information about SNUG Worldwide, including information on your local SNUG event: http://www.snug-universal.org
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