Innovative Ideas for Predictable Success
      Volume 2, Issue 4


   Industry Insight
Spotlight Low Power Methodology Demystified
Synopsys and ARM introduce the Low Power Methodology Manual (LPMM) – a how-to guide for managing power in SoC designs. Phil Dworsky and Ian Thornton explain why the LPMM is a must-read for anyone designing, or getting ready to design, SoCs for low power applications.

With the explosion of the number of wireless devices, the demand for increased functionality of those devices, as well as skyrocketing energy costs, managing SoC power has become an economic imperative for the success of almost every chip company. As companies move to process technologies of 90-nm and below in pursuit of economic advantage, the design challenges are compounded. Through enhanced tools, IP and the LPMM, ARM and Synopsys aim to make what was formerly the domain of only leading edge designs and designers available to the designers of mainstream SoCs requiring aggressive power management in the current or next designs.

The LPMM authors, all low power design experts, are led by Michael Keating, Synopsys Fellow and principal author of the widely acclaimed Reuse Methodology Manual for System-on-Chip Design, (RMM) and David Flynn, ARM Fellow and the original architect behind the ARM® synthesizable processor and the AMBA® on-chip interconnect protocol. Alan Gibbons, principal engineer and Kaijian Shi, principal consultant, both of Synopsys, and Robert Aitken, ARM Fellow, add their extensive practical and research experience, from system-level design through process technology. Combining their broad commercial experience, deep scientific understanding, silicon technology case studies, and a pragmatic approach, the authors describe design techniques that address both dynamic and static (leakage) power, including methods for power gating and dynamic voltage and frequency scaling.

The LPMM covers in-depth the most current and effective low power design techniques. For each topic, the authors describe the design challenge, provide a technology foundation, and then make specific recommendations as well as caution against design pitfalls.

Written in a practical, easy-to-read style, the book covers a broad range of low power topics including: a background and description of the basic approach to low power design; standard low power methods, such as clock gating, gate level power optimization, multi-VDD and multi-threshold logic; and advanced techniques such as power gating, dynamic voltage and frequency scaling. RTL and architectural considerations for both SoCs and silicon IP are also covered.

A chapter is dedicated to dealing with implementing a multi-voltage, power-gated design that covers issues such as design partitioning, synthesis, multi-corner multi-mode optimization (MCMM), power planning, and power and timing analysis. Another chapter is dedicated to implementation challenges through the low-power design flow, including synthesis, place and route, timing analysis and power analysis.

The book also covers physical IP design considerations, including standard cells, memories and state retention for both flip-flops and memories. It also details the design of the power switching networks. Two appendices provide additional information including circuit design for sleep transistors and power switching networks as well as syntax for the Unified Power Format (UPF) commands used to describe power intent earlier in the book.

Not just a theoretical approach to low power, the LPMM is based on extensive commercial experience in addition to several joint silicon technology demonstrator projects, which are described extensively in the book. In the earlier projects, the team focused on managing dynamic power through clock gating as well as dynamic voltage and frequency scaling. They created SoC technology demonstrators that utilized the ARM Intelligent Energy Manager (IEM™) technology, an ARM processor and Synopsys DesignWare® IP, implemented through a Synopsys low power tool flow. Running real application software, these SoCs demonstrated up to 60 percent energy savings and led directly to enhancements in the companies' IP, tools and reference methodologies.

The most recent silicon, resulting from the Synopsys-ARM Low Power Technology (SALT) project, extended the previous dynamic power management SoC to address static (leakage) power management as well, critical for designs at 90nm and below. The teams demonstrated numerous leakage mitigation design techniques, and also directly measured the impact of each of these techniques. The state retention power gating (SRPG) implementation on the processor was shown to save up to 25x the leakage power compared to normal operating mode. Like the dynamic power SoC projects, the SALT project led directly to enhancements in the companies' IP, tools and reference methodologies (e.g., power gating for the ARM1176JZF-S processor). Findings from these technology demonstrators are outlined in the LPMM.

Early feedback on the LPMM has been very positive and demand for the book has been strong as well. Customers may download a free electronic PDF copy of the book at or The website provides information about how to purchase the print edition from Springer or, including Springer’s volume purchase discount schedule. For those who would like to learn more about the LPMM, the website provides additional background information as well as a place to share new findings and updates and even pose questions directly to the authors. As they hear from readers, the authors also intend to post errata and addenda material to the website.

Phil Dworsky is director, strategic alliances for Synopsys
Ian Thornton is director, solutions marketing for ARM

©2010 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.

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"The LPMM enables broader adoption of aggressive power management techniques. Based on extensive experience and silicon examples with real data, the LPMM provides methodology that every SOC designer can use to meet the difficulties faced in managing the power issues in deep submicron designs."
Anil Mankar,
Sr. VP Worldwide Core Engineering and Chief Development Officer, Conexant Systems, Inc.
"Excellent compendium of low power techniques and guidelines with balanced content spanning theory and practical implementation. The LPMM is a very welcome addition to the field of low power SoC implementation that has for many years operated in a largely ad-hoc fashion."
Sujeeth Joseph,
Chief Architect - Semiconductor & System Solutions Unit, Wipro Technologies
"LPMM is a great vehicle for the design community to learn and apply low power design techniques."
Ed Huijbregts, Ph.D.,
VP Product Development – Design Implementation, Magma Design Automation