Innovative Ideas for Predictable Success
      Volume 2, Issue 3


Synopsys at DAC 2007
Helping You Design the Chip Inside

As applications become more advanced and projects increase in complexity, predictable success can only be achieved if your EDA solutions consistently provide what you need to design the chip inside. At DAC 2007, Synopsys invites you to booth 5278 to see for yourself how its solutions help design teams overcome the toughest challenges and achieve the objectives of next-generation SoC design projects.

At this year's show, Synopsys will concentrate on three key challenges for designers and manufacturers today: low power, accelerating time to entitled yield and system-to-silicon verification. Join Synopsys in San Diego to find out how its comprehensive solutions can help you to address these challenges and provide the fastest path to predictable success.

Low Power
What if you could automate the latest power-saving techniques within your design flow?

Power is a pervasive chip-industry issue. Virtually every chip designed today requires careful power management. Low power design of the chip inside is a source of product differentiation for portable products such as GPS and media players.

Synopsys has held its position of technology leadership in power management for over ten years. Its power management solutions have earned the trust of market leaders over the course of thousands of production designs, while its latest multi-voltage technology has already been verified in silicon with over 25 SoC design tapeouts and many more in progress. Power management now spans the entire Synopsys design flow from system to signoff, including low-power IP, consulting services and expert field support. At DAC this year, Synopsys will present the most comprehensive power management solution in the industry.

To deliver early and consistent power predictability, Synopsys' power management solutions are highly automated and operate within a strong ecosystem; Synopsys works with industry-leading partners to develop IP, modeling techniques and foundry flows that support the Synopsys power management solution. By ensuring correlation from RTL to silicon, across implementation and verification, design teams benefit from reduced iterations and improved productivity.

Synopsys' DesignWare® Virtual Platforms enable power modeling at the system level, providing a relative measure of power consumption on an application-by-application basis using the real applications' software and target OS. This enables the system architect to make hardware-software tradeoffs to minimize power for example, looking at how clock speed increases affect power consumption versus the time it takes an application to complete.

Functional verification of advanced low power designs like those using multiple power domains where power can be switched off in a given domain is extremely challenging. The functional behavior of the logic significantly changes depending on whether a power supply is on or off. Synopsys' VCS® RTL verification solution enables verification of designs with multiple power domains during RTL simulation. It is able to model the functionality of isolation and retention cells so that the design can be correctly simulated when power is shut down and returned.

Synopsys offers advanced and predictable synthesis solutions for low power designs. Design Compiler® 2007 is engineered to improve productivity by providing tight correlation to physical implementation. It uses topographical technology to make the design process more predictable, and delivers superior performance across all design metrics power, performance and area. DFT MAX allows designers to reduce test data and time by 90 percent and accelerate yield ramp-up with accurate diagnoses and links to Odyssey-YMS.

For designers addressing physical design challenges, IC Compiler provides 35 percent faster runtime, larger capacity and increased automation to drive designer productivity. It can be used to optimize die size, to reduce the overall cost of your designs. IC Compiler also incorporates adaptive multi-corner, multi-mode technology, which is the key to achieving fast timing closure especially when deploying advanced low power techniques.

Market-leading signoff tools complete the end-to-end low power solution with PrimeTime®, Star-RCXT™ and Liberty™ NCX. PrimeTime delivers the industry's most trusted timing, SI, power and variation-aware analysis all in one product solution. Liberty NCX provides a complete library characterization system architected for current-source models. It delivers the most comprehensive model QA system. With a reference characterization capability, it provides the fastest path to production quality libraries. Synopsys is committed to enabling the industry with current-source models providing enhanced performance and accuracy in modeling solutions.

Accelerating Time to Entitled Yield
To deliver competitive consumer products, today's engineers must accelerate time to entitled yield for the chip inside. They want to identify, prioritize, and fix yield-limiting hot spots before tapeout, account for process variation in the design phase, and drive higher design yield with manufacturing data.

At DAC, Synopsys will showcase advanced yield solutions that enable this level of control. They are built upon production-proven manufacturing engines.

PrimeYield LCC (Lithography Compliance Checking) is the only tool built with production-proven manufacturing technology used at leading foundries and IDMs. With its accurate analysis, the tool can not only find, prioritize and help fix functional and parametric errors in design but also boost productivity by avoiding false positives. The DAC session will provide a tool demo explaining why major foundry, IDMs and fabless customers have chosen PrimeYield LCC for production.

Synopsys' physical verification solution Hercules™ PVS is the leader in runtime performance and productivity with its production-proven integration with Star-RCXT and IC Compiler. Demonstrating Hercules' continued focus on productivity enhancements, the DAC session will show 3 step or less debug with industry-unique interactive short finder.

Synopsys also offers Seismos, the leading solution for analysis of stress and other proximity effects in strained silicon technologies. Seismos uses models that are based on rigorous TCAD simulations validated by silicon data. Seismos is accurate and efficient. It can handle designs with over a million transistors and can be integrated seamlessly into existing design flows. It covers all major stress sources: STI, ESL/DSL, SMT and SiGe, handles complex geometric interactions beyond a simple LOD model. Seismos also supports threshold voltage variation due to WPE effect.

Another showcased yield solution at DAC this year is Raphael™ NXT, a 3D capacitance extractor that provides silicon-accurate self and coupling capacitances for IC design. Raphael NXT accounts for detailed process effects predominant in deep-submicron technologies. It provides seamless integration with Synopsys' market-leading Star-RCXT, a full-chip parasitic extractor, by extracting 3D capacitance of critical nets, cells and blocks on the full-chip level. It also supports highly scalable distributed processing resulting in significant reduction in runtime.

System-to-Silicon Verification
Designers need verification solutions that achieve predictable success today and that have what it takes to adapt to tomorrow's increasingly complex verification needs. Synopsys provides comprehensive verification solutions that give engineers confidence that they will be able to meet consumers' exacting needs, even on the most advanced designs.

Synopsys leads the industry in this field with its Discovery™ Verification Platform, the most comprehensive system-to-silicon verification solution available. It integrates all of the tools needed to address all critical areas of verification from systems to digital to analog, supporting the proven VMM-based verification methodology for reducing risk in semiconductor design and development.

Synopsys' verification solutions on show at DAC 2007 include Discovery AMS XA, a next-generation technology that enables SPICE accuracy with FastSPICE performance. HSIM and Nanosim feature tightly integrated mixed-signal verification solutions that have been adopted in over 100 customer production flows to date.

Likewise, hundreds of teams globally have adopted Synopsys' next-generation VMM solution, the industry-leading SystemVerilog methodology. VMM Planner, VMM Applications and VMM automation deliver even higher predictability and productivity.

Synopsys' System Level Solutions, including Virtual Platforms allow design teams to develop software pre-silicon and integrate code continuously with hardware while it is still being designed. They provide software-driven power/performance optimization and system validation.

Saber enables system-level verification of complex multi-domain systems, and offers virtual prototyping to reduce design cycles and time to market.

Partner Solutions
Synopsys is partnering for predictable success. DAC visitors will be able to see for themselves how its partnership with ARM is enabling a fast track to lower power and streamlining SoC design from ESL to GDSII. Synopsys is also working alongside HP on solutions for accelerating physical verification, and together with TSMC is developing ways to integrate design and process

In a series of go-deep sessions Synopsys will explore a range of topics:

  • TSMC solution (foundry/8.0 reference flow/libraries)
  • Common Platform Partnership solution (foundry/reference methodology/libraries)
  • VR libraries (CCS)
  • ARM libraries (CCS)
  • UMC solution (foundry/reference methodology/libraries)
  • ARM 1176 low power implementation case study
  • ARM Cortex-A8 low power implementation case study

Helping You Design the Chip Inside
As a world leader in EDA, Synopsys is dedicated to helping you design the chip inside, providing comprehensive solutions that meet designers' toughest challenges in the production of complex SoCs.

Synopsys' three initiatives for DAC 2007 low power, accelerating time to entitled yield, and system-to-silicon verification are geared towards achieving this with comprehensive solutions that provide the fastest path to predictable success.


©2010 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.


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-   Synopsys at DAC 2007