| Customer Spotlight|
Redpine Signals Differentiates with
With a product range aimed squarely at the wireless convergence market, Redpine Signals’ expertise is centered on ultra-low-power design. Venkat Mattela, Chief Executive Officer explains why Synopsys was chosen to provide a robust and accurate low-power design flow.
With a development center in Hyderabad, India, and corporate headquarters in San Jose, California, Redpine Signals is one of a few recent startups from India to have made a successful debut as a product development company.
What’s more, Redpine’s target market is the competitive world of ultra-low-power wireless convergence products. “We operate in a highly competitive environment,” states Venkat Mattela, CEO at Redpine Signals, “and to be successful it’s important to be very clear about the business value that you offer.” For Redpine, innovative design and efficient implementation technology underpin their competitive business advantage.
Low Power from Architecture to Implementation
Redpine’s wireless platforms are built upon differentiating technology that includes ultra-low-power OFDM (Orthogonal Frequency Division Multiplexing) and MIMO (Multiple-Input-Multiple-Output) -based wireless architectures, as well as multi-threaded processing engines. Implementing standards-compliant wireless technology enables delivery of application-aware ultra-low-power wireless connectivity. “Our architectures are designed for low power from the outset,” explains Mattela. “Our customers, the leading equipment and device manufacturers, care about battery life as well as robustness, range and data rates.”
When operating at suboptimal ranges or in hostile environments, wireless communication systems often downshift to more robust but lower data rates, which results in excessive battery drain for transferring a given amount of data. To counter this, Redpine’s aim is to improve wireless performance without a major increase in chip size. This requirement is a strong driver for their move to a low power design flow.
As a fabless vendor, Redpine understands the critical importance of optimal semiconductor implementation into the target process geometry. Mattela continues: “The effort we put into semiconductor implementation gives us an additional competitive edge, and is a further opportunity to optimize for power. This is where we look to Synopsys for a complete low-power implementation and verification solution that enables our designers to achieve the design goals we set.”
The Redpine design team is experienced with Synopsys implementation and verification solutions, having completed a number of designs with Design Compiler® RTL synthesis tool, PrimeTime® static timing analysis tool and VCS® verification solution. Redpine has recently used a testchip to evaluate the Synopsys’ low power solution.
“Our goal with the evaluation was twofold: first, to see how much power could be saved by applying optimizations during implementation, and second, to verify the power sign-off accuracy by comparing the analysis tools against our test chips,” explains Mattela.
During the benchmarking exercise, Redpine also benefited from the presence of the experienced, local Synopsys support team.
Redpine, with the support of the Synopsys team, used Power Compiler to synthesize clock-gating and perform gate-level power optimization. The results were impressive. At low levels of activity – just one percent of nodes toggling – the optimized design reduces dynamic power by almost 17 percent compared to the original design and reduces area by almost five percent. With 50 percent of nodes toggling, the dynamic power is reduced by over 66 percent while the area saving is over five percent.
Table 1. Dynamic power saving achieved with Power Compiler
The results of the PrimeTime PX analysis are equally notable. Depending on which period of simulation activity is measured, the correlated difference with the measured silicon varies between 0.5 percent and 1.7 percent – well within the limits set by the Redpine engineers.
Table 2. PrimeTime PX correlation with Test Chip silicon
“We were delighted with the improvements in both the power figures and the core area, and PrimeTime PX gives us signoff-accurate analysis for power measurements.” continues Mr. Mattela. “In fact, the optimizations we made with Power Compiler helped to improve our end-product differentiation on a wireless LAN core, which was a key factor in influencing two customers to select our technology over competitive solutions.”
Looking forward, Redpine knows it must stay ahead of the curve in hardening its designs as they move to 90nm and 65nm processes. This also means moving forward with advanced power-saving techniques that minimize leakage power as well as dynamic power. The fact that the Synopsys low-power implementation and verification solution supports advanced low-power techniques today was a further factor in Redpine’s decision to select the Synopsys low-power solution.
But technology was not the only factor influencing Redpine’s decision. The presence of local high-quality technical support is of critical importance to them. Furthermore, Synopsys fully understands Redpine’s business situation. According to Mattela, “We have developed a partnership with Synopsys that has grown with us since our startup days. Our next-generation products target mobile and consumer applications for emerging wireless standards. Synopsys technology and support is critical in enabling us to deliver the smallest silicon and system footprints in the industry.”
For now, Redpine Signals is looking forward to the next phase of company growth, developing the business by securing further design wins with global customers, and advancing their product line through architectural innovation and excellence in design implementation.
About Redpine Signals
Redpine Signals is a fabless semiconductor company with a mission to create ultra-low power wireless convergence products targeting next generation mobile and consumer applications.
Redpine Signals’ experienced team has developed multiple patent-pending implementations of standards compliant wireless technology to deliver application aware ultra low power wireless connectivity which dramatically improves battery life on mobile devices as well as uses advanced MIMO techniques to improve robustness, range, and data-rate.
The company is headquartered in San Jose, California and has a state-of-the-art development center in Hyderabad, India.
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