Innovative Ideas for Predictable Success
      Volume 2, Issue 2


  Partner Solution
Spotlight Automating Multi-Voltage Design in a Reference Flow
Mort Bambad, Senior Director, Corporate Marketing at UMC, and Paul Lai, Group Manager Strategic Alliances, Synopsys, outline the advanced design practices encapsulated within the new and improved multi-voltage UMC 90-nanometer (nm) reference design flow.

The use of a reference flow benefits design teams in several ways. Fundamentally, a reference flow automates building of the manufacturable design. The ability to easily re-build a design after making a modification increases productivity and eliminates design process errors with little manual intervention. The availability of a familiar design process, with a consistent structure for design scripts and data also improves designer productivity. When the consistency extends to reports and log files, a reference flow also supports design audit, further boosting design quality. These benefits help design teams to reduce development risk and improve implementation predictability for even the most complex designs.

UMC Reference Design Flow
UMC and Synopsys first announced the 90-nm reference design flow, optimized for low-power system-on-chip (SoC) designs, in November 2005. The validated RTL-to-GDSII hierarchical design flow is based on Synopsys' Galaxy™ Design Platform, UMCís standard cell library, and UMC's 90-nm process. It addresses leakage power challenges at 90-nm and provides advanced design-for-manufacturing (DFM) capabilities for faster yield ramp and lower development costs.

The UMC-Synopsys reference design flow incorporates many of Synopsys' Galaxy Design Platform's low-power, design-for-test (DFT) and design-for-manufacturing technologies, including Power Network Synthesis (PNS) and Power Network Analysis (PNA), which are used to design power plans at the floorplanning stage. Other floorplanning capabilities include virtual flat floorplanning with physical hierarchy-aware global routing, virtual timing optimization, and macro placement with automatic hierarchy detection. Designers create an optimized initial design floorplan using these advanced features to guide them to the next design steps in physical implementation. By following this process, design teams can achieve faster timing closure and avoid design iterations.

The reference design flow also features multi-threshold optimization to take advantage of UMCís 90-nm multi-threshold (multi-Vt) libraries for leakage and dynamic power reduction. In addition, the flow supports advanced signal integrity capabilities to perform analysis for electromigration (EM) and voltage drop (IR) that are crucial in avoiding design failure at 90-nm and below.

Support for DFM
The UMC-Synopsys reference design flow incorporates several DFM capabilities that provide appropriate manufacturing support for UMCís process technology. One example is the addition of timing-driven dummy metal insertion to specifically meet UMC's metal density requirements while maintaining timing closure, and automatic redundant via and via farm insertion. These new DFM capabilities help designers to improve reliability and are supported in Synopsys' place-and-route solution.

Figure 1. UMC-Synopsys 90nm Multi-Voltage Reference Flow Diagram

MultiVoltage Design Challenges
Several recent enhancements have been made since the introduction of the original advanced low-power reference design flow. One of the main improvements is the introduction of an automated multi-voltage (multi-Vdd) capability that can help to significantly reduce dynamic power and leakage power dissipation.

Implementing multi-voltage capabilities within the reference flow requires a total approach to be taken. Once level shifter (LS) cells have been inserted into the design, every subsequent step from synthesis and DFT to physical verification must be multi-voltage aware.

Level Shifter cells follow a two-stage insertion process in Design Compiler (Figure 2). At the pre-synthesis stage, the LS cells are inserted in the GTECH netlist. Sub-blocks operating at 1.2V are grouped and operating conditions set on each voltage area, enabling L2H and H2L LS cells to be inserted automatically in the correct voltage areas.

Figure 2. Implementing Multi-Voltage with Level Shifters

Enhanced DFT
Several additions to the DFT capabilities within the reference design flow help design teams reduce risk and achieve predictable success for complex low-power designs. The DFT process supports multi-voltage design, enabling LS cells to be inserted into the existing scan chain incrementally. Synopsysí DFT MAX scan compression automation solution is now included in the reference flow to enable higher test quality and to significantly reduce test application time. By using adaptive scan compression techniques, DFT MAX enables a 10-50x reduction in test time with minimal area and timing impact.

Test Chip Validation
To validate the effectiveness of the reference flow, consultants from Synopsys Professional Services collaborated with UMC engineers to design a representative test chip with an open source 32-bit RISC microprocessor core. The test chip, which was validated with UMCís library, was partitioned into multiple voltage regions and implemented using the UMC-Synopsys advanced low-power reference flow. The core consists of a SPARC V8 32-bit RISC processor, industry standard AMBA system buses, 10/100 Ethernet MAC and standard PCI interfaces. The chip is highly configurable and expandable for additional digital and/or analog/mixed-signal intellectual property (IP) modules.

Figure 3. LEON Multi-Voltage UMC Test Chip Voltage Domain Configuration

Silicon validation of the UMC-Synopsys reference flow is an important proof point in demonstrating that the performance and capabilities of the Galaxy Design Platform work smoothly in UMCís process flows. This approach ensures that Synopsys and UMCís mutual customers have access to a proven and robust design flow that targets low power, DFT and DFM requirements.

The UMC-Synopsys reference design flow is available today and can be accessed from UMC's website The reference design flow was jointly developed by UMC and Synopsys Professional Services.

About UMC
UMC is a leading global semiconductor foundry that manufactures advanced process ICs for applications spanning every major sector of the semiconductor industry. UMC delivers cutting-edge foundry technologies that enable sophisticated system-on-chip (SoC) designs, including 90nm copper, 0.13 micron copper, embedded DRAM, and mixed signal/RFCMOS. UMC is also a leader in 300mm manufacturing. In addition, UMC is a leader in 300mm manufacturing with strategically located 300mm fabs to serve a global customer base: Fab 12A in Taiwan and Fab 12i in Singapore. UMC employs over 12,000 people worldwide and has offices in Taiwan, Japan, Singapore, Europe, and the United States.

©2010 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.

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Author Bios
Mort Bambad is Senior Director, UMC Corporate Marketing at UMC. Prior to UMC, Mort was the VP of Marketing and Business Development of 1st Silicon. Before that he worked for TSMC for over five years as Senior Business Development Manager. Mort spent three years at Wacker Siltronic, a raw silicon wafer manufacture in the UK and Germany. He also held various managerial positions at Philips Semiconductors for 9 years. Mort began his Semiconductors career at University of Westminster in the UK in 1984, where he did research into integrated circuit design methodology and CAD applications. He graduated with Honours from the same University.

Paul Lai is Group Manager Strategic Alliances, Synopsys and a veteran in the EDA industry with over 15 years experience. Prior to Synopsys, he held various management positions in applications, marketing, and strategic programs at Gateway Design Automation, Cadence, and Viewlogic. Currently, he manages the Synopsys strategic alliance program with key foundries. Paul earned B.S.E.E. and M.S.E.E degrees from Texas A&M University and an MBA degree from the University of California, Berkeley.


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