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Transaction-Level Co-emulation Added to VMM Methodology
Engineers can now use advanced SystemVerilog verification methodologies to achieve higher productivity with hardware assisted verification platforms. Synopsys and EVE have collaborated to bring together hardware acceleration and high-performance functional verification using the popular VMM methodology. Alain Raynaud, technical director, EVE, and Mehdi Mohtashemi, verification group R&D director, Synopsys, describe how support for transaction-level modeling enable these key verification technologies to be integrated efficiently.
The SystemVerilog language offers a rich set of features that has significantly enhanced the quality and productivity of verification. Engineers now have the ability to verify their designs using assertions that are built in to the design, to generate large volumes of test scenarios with constrained-random stimulus, and to measure verification quality with functional coverage. Industry best practices for these techniques have been documented in the best-selling book Verification Methodology Manual for SystemVerilog, and its VMM methodology. Used within the VMM methodology, SystemVerilog is now the heart of a powerful, productive verification environment for a growing number of engineers.
The VMM methodology benefits chip development teams with clear rules that define how to create a powerful verification environment quickly and then become productive with it. All teams, whether local or remote, within one company or across a number of organizations, benefit from the interoperability of a VMM-compliant environment, and the ability to share commercially available VMM-aware verification IP, expertise, and compliant tools.
These industry-wide VMM economies of scale further enhance verification productivity and quality. Many design teams report that the VMM methodology improves productivity, saving weeks or even months of chip development time -- starting from the first project.
Next-Generation VMM Solution
The next-generation VMM solution builds on the proven foundation of the VMM methodology with three new components: VMM Planner, VMM Applications, and VMM Automation. VMM Planner enables managers to systematically plan and track verification progress to increase verification visibility and predictability; VMM Applications reduce testbench creation time by allowing architects to more quickly construct effective verification environments; and VMM Automation improves the productivity of engineers developing and using advanced testbenches.
VMM Hardware Abstraction Layer
The VMM Hardware Abstraction Layer (HAL) is a VMM Application. It includes a class library that supports transaction-level co-emulation between the hardware-accelerated design and a VMM-compliant testbench that runs on a SystemVerilog simulator, such as Synopsys’ VCS functional verification solution. VMM HAL also supports the OpenVera language. A key benefit of the VMM HAL is that it maximizes reuse of the testbench code, since the top layers of the verification environment -- Tests, Generators and Transactors -- do not need to be modified. Only the lower layers Monitors and Drivers need to be made HAL-compliant [see figure below].
Figure 1. HAL-compliant transaction level testbench
The hardware abstraction layer enables different hardware acceleration platforms to be used with the same constrained-random testbench used in simulation-only environments. Testcases and DUT can target different hardware platforms without any modifications. Among the first products to take advantage of this capability is EVE’s ZeBu family of emulators.
The VMM HAL application also contains a purely simulated implementation of the hardware abstraction layer that allows the testbench and testcases to be developed and debugged with the DUT entirely within the same simulation, without modifications and does not require accessing the hardware emulator. The VMM HAL environment can target hardware or simulation at runtime through the use of a simple simulator command-line switch.
Need For Co-Emulation
Hardware emulation and simulation acceleration allow verification engineers to speed up verification runs that would otherwise be more difficult to achieve with other technologies. Hardware-assisted Acceleration can simulate multiple frames of HDTV content and other realistic graphics applications representing hundreds of millions of cycle per testcase. For instance, reference frames for various video compression schemes can be processed in minutes.
Emulation is also used to bridge the gap between hardware and software design. Booting an operating system on an embedded processor device or testing the reset sequence of an SOC with the actual production firmware proves invaluable in finding HW/SW integration issues during pre-silicon validation.
Benefits of Interfacing at the Transaction-Level
The VMM HAL specifies the interaction between the testbench and the DUT at transaction-level, the Monitors and Drivers layers acting as smart adapters between transactions and signal-level protocols. Previous co-emulation approaches had relied on synchronizing the testbench and the DUT at the signal or event level, which proved to be very inefficient as the emulator and simulator had to run serially and synchronize at every simulation event.
By raising the level of abstraction to transactions instead of signals, the emulator is now able to run at full speed, which can exceed 20 MHz, without sacrificing accuracy and still be completely under the control of a VMM based testbench. The co-emulation link can stream data between the design and the testbench at up to 800 Mbit/s, enough for even the most data-intensive applications. The conversion between transactions and cycle-accurate signals is performed in hardware by the synthesized portions of the Drivers and Monitors layers.
Creating Acceleration-Friendly Testbenches
The monitors and drivers that are interacting with the design under test (DUT) need to be split in two parts: a synthesizable BFM that converts transactions into cycle-level activity on ports of the DUT, and a SystemVerilog layer that feeds transactions to the BFM and presents the same software API to the rest of the testbench as the original behavioral monitor and driver. The rest of the testbench can therefore be reused with no modifications.
The key to running transaction-level co-emulation at high speed is to process the compute-intensive part of the transactor in hardware within the accelerator, rather than using software on the host workstation. To do so, the transactor is coded as a simple synthesizable state machine, or BFM, that receives messages and converts them into signals that are connected to the design ports or internal buses. The synthesized part of the transactor is mapped onto acceleration hardware. The VMM HAL specifies the protocol that the BFM must follow in order to exchange messages with the testbench. It only uses three simple Verilog macros to implement all communication, keeping the design of the BFM as simple as possible.
Summary: Performance and Control
Transaction-level co-emulation combines the powerful capabilities of the VMM Hardware Abstraction Layer application and its proven VMM methodology foundation with the improved performance levels of hardware acceleration.
Providing support for transactors in the VMM HAL application enables optimization of the simulated testbench by raising the level of abstraction so that the interconnect is no longer a bottleneck when interfaced with hardware accelerators. The very high bandwidth between testbench and accelerator is the key to delivery of very high verification throughput for the entire system. Furthermore, transactor-based design is cycle-accurate and supports testbench portability and reuse.
The VMM HAL application is a feature of Synopsys’ VCS solution, and is available now. Support for transaction-level co-emulation within the VMM HAL application is the result of close technical collaboration between Synopsys and EVE.
About the Authors
Alain Raynaud is the Technical Director of EVE-USA, Santa Clara, Calif. Prior to joining EVE, he was in charge of advanced verification methodologies at Tensilica Inc. He holds two patents on accelerated verification awarded while with the Emulation Division of Mentor Graphics. Alain Raynaud holds an MS in computer science from the University of Illinois at Urbana-Champaign and from Supélec, France.
Mehdi Mohtashemi is the R&D director in verification group at Synopsys and has more than 20 years of experience in electronic circuits, system design, validation and software development. At Synopsys, he has been involved with test-bench and verification-automation tools and methodologies development.
Mehdi holds an MS in Electrical Engineering and Computer Science from Stanford University and a BS in EECS from UC Berkeley.
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