The Three Ps: Key Characteristics for Success
What is it that drives the semiconductor industry to success? Aart de Geus, CEO and Chairman, Synopsys, explores recent trends in process geometry development, and the growing number of technical challenges that designers face – both in India and globally.
With an increasing proportion of designs targeting advanced processes across a broad range of applications, the Indian design community has become truly representative of the global design landscape,
We have some good indicators that illustrate the trends very well. The attendance at the Synopsys (SNUG) India user group has increased dramatically over the past few years. Numbers are up from 250 engineers in 2002 to over 800 in 2005, and over 1000 attendees are expected for the 2006 event. This is astounding growth, which truly reflects the development of the semiconductor design industry in this region. To provide more context, these figures are second only to the latest attendance at our SNUG San Jose meeting in the heart of Silicon Valley.
It’s not just quantity though that characterizes the design landscape in this region. There is clear evidence of quality and innovation taking place. Our data tells us that the majority of design starts in 2005 were targeting 90nm processes, We expect this transition to continue to 65nm and beyond, In fact, during 2005, 12 percent of design starts in India were already targeting 65nm geometries compared with around 7 percent globally. This is a strong indication that this region is ahead of the curve when it comes to advanced design. It is the technical and economic issues that accompany the move to these advanced geometries that is now driving Synopsys’ strategy.
The 'Three Ps' Framework
Designers have become adept at meeting evolving requirements as they transition from one chip development project to the next. While new challenges emerge, some of the success factors have remained constant for some time. The ‘three Ps’ framework encapsulates the key issues.
The first of these is performance. In the widest sense, performance typically focuses on three optimization functions: speed, area and power. Over the last 40 years, the raw performance of many chip designs has remained a key characteristic for success. The second P is productivity, by which is meant the cost and engineering effort built into reaching a certain objective. The importance of productivity has grown dramatically in the last few years.
These first two Ps always trade off against one another: you can easily increase productivity by reducing the device speed, for instance. Our third characteristic, then, is predictability – the statistical variation on the other two Ps. In other words, bringing a product to market on time and within budget.
The focus on each of the three Ps varies according to who you are speaking to within a company. Typically, the engineers concentrate on performance: they want to know if they can get the speed that they need (or meet the power budget). Middle management is usually concerned about productivity: they want to know how much budget they have, how much effort it will take, and when they can get the speed that they need. The top level of management focuses on predictability: they want to know if they will ever get to the speed that they need. They want to ensure that they fulfill their commitment to their customers and that the chip is rolled out successfully and on a timely basis.
Facing Technical Challenges
The three Ps model provides three axes upon which solutions can be developed. Needless to say, there are many technical challenges to overcome. The first of these is verification, which is often cited as taking 60-65 percent of the overall design time. Here, the challenge is that the problem is growing far more rapidly than Moore’s Law. The obvious quick fix is to use significant pre-verified IP that works really well, but if the IP doesn’t work you have an even bigger problem.
Figure 1: The Three Ps of Predictable Success
A second big challenge is timing and optimization – we have been living with this problem for a while, and have some effective strategies in place. Signal integrity is also an important concern – while it pushes the traditional digital paradigm more and more towards an analog problem, our job is to push it back – because it’s really in digital design that we’ve seen the biggest improvement in productivity in the last 40 years.
Then there are power-related challenges to overcome. In one sense, timing and power have become equivalent optimization factors: most people would say that, at this point in time, the increases in speed are primarily limited by the ability to dissipate the power or to get the power where it’s needed. By power, we refer to both dynamic power and leakage power. Of course, dynamic power grows with the number of transistors and with the frequency. Although we’ve brought the voltage down in the last ten years, we’re trying to bring it down much further. Leakage power is now a very important ingredient at the smaller geometries of 90nm and 65nm.
In the design for manufacture (DFM) arena, there are problems concerning printability, mask-making and the actual yields achieved when you are in manufacture. Here, the challenge is that the feature size is now significantly shorter than the wavelength of light. The wavelength of light is 193nm and yet we’re talking about routinely manufacturing 65nm transistors and below.
Synopsys Strategy for Predictable Success
The technical challenges described above have driven a number of changes in Synopsys’ products. Fundamentally, our current strategy reflects the fact that these problems are now completely interdependent, and each must be dealt with as part of the bigger picture.
If there’s one very strong link that’s necessary, it is the link between implementation and DFM. As we transition to smaller geometries, and it becomes possible to put more and more functionality on a chip, some shortcuts are needed in order to design all of this functionality within a reasonable timeframe. IP reuse is an obvious shortcut that is very much in use today. One of the key requirements is to make sure that the IP is of the highest quality.
The clear need to have more optimized flows is the essence of the Synopsys strategy of the last six or seven years. We recognize the importance of having a complete solution where all the pieces correlate together and are capable of optimizing simultaneously and concurrently to meet the design targets. Synopsys tools address this requirement: Galaxy for implementation, Discovery for verification, a comprehensive set of IP solutions, and a set of tools for DFM.
The Need to Optimize Design Flow
To drive the industry to success at smaller geometries, we have to address how best to optimize the design flow, how to boost verification, and how to increase predictability. With a complete and correlated flow that recognizes the fact that design issues are interdependent, it will be easier to achieve these goals on the path to 65nm and beyond.
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