Synopsys Delivers Successful Professors’ Lecture Tour across China
Following a similar initiative in 2004, Synopsys recently assembled a panel of renowned technology experts to deliver a series of talks to the Chinese IC design community.
Three Synopsys technology experts were joined by Dr. Michael Lightner, President and CEO of the Institute of Electrical and Electronics Engineers (IEEE), and Dr. Giovanni De Micheli, Professor and Director of the Integrated Systems Centre at EPF Lausanne, Switzerland, to deliver a series of informative seminars to Chinese academics and industrialists.
Dr. Lightner’s objective was to inform the audiences about the role of the IEEE in enabling the standards process, and the IEEE’s plans to expand operations in China. Dr. De Micheli looked to the future technologies that will eventually replace CMOS.
Professor Wolfgang Fitchner, Vice President and General Manager of the Synopsys TCAD Business Unit and professor at the Integrated Systems Laboratory Department of Electrical Engineering, Swiss Federal Institute of Technology, explained how widespread access to powerful computers has changed the approach to research and development in electronics.
Professor Fitchner was joined by Dr. Thomas Williams, a Synopsys Fellow and test expert, and Dr. Charles Chiang, a Synopsys Scientist with expertise in design for manufacturability.
The lecturers toured several key technology locations, including Beijing, Hangzhou and Shanghai. They delivered insight to the prestigious Chinese Academy of Sciences, taught advanced IC courses for young professors from 21 top Chinese universities, held round table discussion with education groups and industrial groups, held meetings with several Synopsys customers and had discussions with executives from the Chinese Ministry of Information Industry.
The overwhelmingly positive feedback from the audiences across China confirmed the value of Synopsys’ investment in delivering the ‘Professors’ Tour’. Initiatives such as this are a vital ingredient in the drive to share best practice in IC design and the business of semiconductor development, encouraging controlled growth of the IC industry in China. The discussion topics are explored below in further detail.
IEEE Objectives in China
Dr. Lightner explained that the IEEE is the world’s largest technical professional organization. It has a strategic initiative to greatly expand activities in China. This includes forming an office in Beijing staffed by Chinese nationals, expanding its accreditation support activities with various universities throughout China, expanding the offering of its software certification program CSDP (Certified Software Development Professional), working to integrate more Chinese companies as key players in the international standards program, increasing the number of international conferences held in China, and exploring with Chinese engineers, academics and industry leaders how the IEEE can be of increasing support to technical professionals in China. In addition, the IEEE recognizes that it must further interact with participants to better understand the activities that will support their development and success as technical professionals in a globally competitive environment.
Nanoelectronics: Challenges and Opportunities
Looking very much to the future, Dr. De Micheli talked about the challenges of adapting to life after the scaling of CMOS technology has come to an end. It is unclear whether CMOS devices in the 10-20 nanometer range will find a useful place in semiconductor products. At the same time, new silicon-based technologies (e.g. silicon nanowires) and non-silicon based (e.g. carbon nanotubes) show the promise of replacing traditional transistors. In this scenario, there are multiple challenges to face, like the production of nanoscale CMOS with reasonable yield and reliability, the creation of newer circuit structures with novel materials as well as the mixing and matching of older and newer technologies in search of a good balance of costs and benefits.
Computational Electronics: Past, Present and Future
Professor Fitchner discussed the ways in which widespread access to powerful computing facilities has changed the approach to semiconductor electronics research and development, away from time-consuming trial-and-error experiments to utilization of modeling concepts, based on first-principles with physical foundations. This shift offers unique advantages over the original experimental techniques.
Design for Testability: The Path to Deep Submicron
Design has never been simple, but at 90 nm and below – and definitely at 45 nm – it is becoming increasingly difficult. Process and lithography issues continue to drive the advance to new technology nodes. Due to the effects of scaling, defect mechanisms are no longer easily identified with single “stuck at” fault models but mandate a far more complex and challenging solution. Dr. Williams looked at these new demands on delay testing and how quality can be improved. He also addressed the question of how compression will play in this arena. The area of design for manufacturing (DFM) and design for yield (DFY) are now also taking hold as new issues that must be addressed during the design phase. Manufacturing and test are beginning to develop an even stronger relationship due to the close interconnection between yield ramp-up and diagnostics, supported by DFT structures included in the design.
Design for Manufacturability (DFM)
Dr. Chiang introduced the concept of yield loss on three major factors in 65nm and below technology. These included random defects due to particles, shape variation due to lithography, and thickness variation due to Chemical Mechanical Polishing (CMP). Dr. Chiang examined the solutions present for each yield loss factor, including both analysis and optimization.
©2010 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.