Innovative Ideas for Predictable Success
      Volume 1, Issue 2


Spotlight Synopsys Technology 'Sizzles' at DAC 2006
Missed DAC this year? Here's a round-up of the hot technology and topics featured in Synopsys' DAC line up for 2006.

This year's Design Automation Conference, held in San Francisco, provided a platform for the announcement of a number of important product initiatives from Synopsys. But Synopsys' commitment to the 2006 Electronic Design Automation (EDA) showcase event was not just about products. Engaging with customers, understanding their needs, and offering technical expertise were the underlying themes for the show.

Predicable Success Means Productivity, Performance and Predictability
At the 43rd annual DAC, Synopsys' solutions were focused on delivering predictable success to help enable customers to achieve their productivity, performance and predictability goals. Synopsys recognizes that customer success depends on:

  • achieving the high levels of performance that they need in order to differentiate their products;
  • maximizing their engineering resources and reducing manufacturing costs;
  • reducing risk and delivering successful results in terms of chip economics.

Performance, productivity and predictability are the key ingredients to a successful design outcome.

How will Synopsys deliver predictable success? The DAC announcements, presentations and demonstrations provided evidence of the leading technology and services that Synopsys offers in support of this position.

Tech Experts at DAC
Five of the world's leading technology experts enlightened visitors at the Synopsys booth with in-depth technology talks on yield and DFM, low power, design-for-test, verification methodology and approaches to managing design complexity. These popular sessions demonstrated that the DAC audience has a strong desire for technical knowledge, as well as gathering new product information.

Design for Manufacturing
One of the hot topics at this DAC has been Design for Manufacturing (DFM). Raul Camposano, Synopsys CTO, cited the value of DFM in a DAC panel session. "The full benefit of DFM is only realized by increasingly integrating what needs to happen in the fab (mask synthesis, yield management, test chips, TCAD) with a new generation of manufacturability enabled design tools," explained Dr. Camposano.

Synopsys' most significant technology announcement at DAC substantiated Dr. Camposano's assertion. PrimeYield, a new DFM tool suite for design-yield analysis, accelerates the time to entitled yield. PrimeYield accurately predicts design-induced mechanisms that threaten yield in highly sensitive process areas, and provides automated correction guidance to upstream design implementation tools. The primary value for the designer is reduced time to entitled yield. Anantha Sethuraman, Synopsys' Vice President of DFM marketing, defines entitled yield as "the point when a design starts to pay back the capital investment made in the product".

Momentum in Implementation
Continuing on the DFM theme, DAC saw the announcement of two new Synopsys tools to address the challenges of variation-aware design. PrimeTime® and Star-RCXT™ have been extended with new statistical capabilities for to provide a variation-aware design solution for sub-65nm processes. PrimeTime VX and Star-RCXT VX bring the power of statistical analysis to the EDA industry's most widely used and trusted timing sign-off solution. This new capability allows customers to reduce margins, improve design robustness, and enhance parametric yield. More than 250 people attended a lunch event where Synopsys, Qualcomm, STARC, and TSMC executives shared their perspectives on the challenges posed by increasing process variation in sub-65nm designs. And many of these attendees learned more details about the PrimeTime VX and Star-RCXT VX sign-off solution by attending the related demo suite sessions.

Raphael™ NXT was highlighted in the DFM demo suites. Raphael NXT is a true three-dimensional capacitance extractor that provides silicon accurate self and coupling capacitances for IC design. Equipped with an ultra-fast extraction engine, Raphael NXT complements Star-RCXT by extracting 3D capacitances of critical nets, cells or blocks on the full-chip level.

With PrimeYield, variation-aware tools and leading extraction technology, Synopsys provides a comprehensive set of DFM tools that enables designers to assess process variability effects at the design stage.

Synthesis Redefined
Synopsys continues to redefine synthesis, adding topographical technology to Design Compiler® Ultra, bringing the benefit of better synthesis predictability and faster time-to-market. The momentum of Synopsys' DFT MAX scan compression solution continues to rise, with the recent announcement of more than 50 tapeouts.

Synopsys next-generation physical implementation solution, IC Compiler, was featured in a special DAC "Customer Successes in Silicon" event where senior designers from Conexant, Micronas, STMicroelectronics, STARC, Texas Instruments, and Toshiba discussed their experiences in applying IC Compiler to real-world tapeouts in front of a record audience of more than 350 people. The presenters clearly demonstrated that IC Compiler is delivering tapeout success for all process nodes today. Commenting on the event, Dr. Chi-Foon Chan said, "This is the best DAC event of its kind that I have attended in quite a while. The attendance was strong and the presentations very compelling. It is hugely gratifying to see this level of live endorsement from multiple key customers traveling from all main regions — not only North America locally but also Japan, India and Europe. Clearly, IC Compiler is on a roll." IC Compiler also drew large audiences in the Next-Generation Physical Design and Designing for High Yield demo suite sessions in the Synopsys booth.

Faster Verification with SystemVerilog
Adoption of SystemVerilog continues and the benefits are increasingly seen at the design level. Synopsys' SystemVerilog user forum luncheon featured presentations from ARM, Cisco, Sun, Tensilica, Texas Instruments and Transmeta. Highlights included Tensilica reporting 5X-8X code reduction using SystemVerilog design constructs and Transmeta achieving 10X faster simulation using high-level SystemVerilog models. Synopsys underlined its verification leadership position at DAC in both technology and performance, with a number of presentations and demos.

Synopsys scientist Janick Bergeron's sell-out DAC presentations were aimed at helping designers get the best out of SystemVerilog. He discussed the motivation for using a standard methodology ("Don't re-invent the wheel!"), the benefits of a robust methodology ("Productivity!"), and some highlights of the Verification Methodology Manual (VMM) for SystemVerilog. The VMM book has established itself as one of the fastest-selling EDA publications of all time according to publisher Springer Science+Business Media, and has spawned a vibrant ecosystem of companion books and training including a course offered by the University of California.

Verification demos highlighted the 5X performance advantage of VCS® with Native Testbench (NTB), assertions, formal analysis and unified coverage. The strength of Synopsys' verification solutions was in evidence with demos around transaction level verification with SystemC™ and SystemVerilog, and a showing of the Synopsys comprehensive SystemVerilog design and verification flow.

Synopsys teamed with training specialists Doulos to provide a DAC solutions workshop on SystemVerilog Testbench Productivity with the VMM methodology.

Tape-Out Proven Low Power Solutions
Synopsys partnered with ARM and TSMC to hold a DAC luncheon event on "Low Power Design Proven Technology". Low power continues to be a dominant concern for many design teams and this panel brought together experts in IP semiconductor process, tools and methodology to present the challenges and proven solutions for implementing high-performance, low-power System-on-Chips (SoCs).

Mixed-Signal Design
At this year's DAC, Synopsys showcased its strong line-up of Analog Mixed-Signal (AMS) solutions, and held a number of key AMS focused events. In honor of HSPICE's 25th Anniversary, the AMS Breakfast included a number of distinguished panellists, including Dr. A. Richard Newton, Dean of the College of Engineering, University of California, Berkeley and Shawn Hailey, founder of Meta-Software. The panellists discussed how the future of circuit simulation and modelling will evolve to meet the challenges created by new process technologies, emerging markets and advanced computing architectures. The Synopsys Interoperability Breakfast panel, that included such industry luminaries as James Solomon, Jim Hogan and Philippe Margarshack, examined the benefits and challenges of enabling interoperability for custom design through OpenAccess.

In the demo suites, the focus was on addressing the challenges of designing today's and tomorrow's mixed-signal SoC integrated circuits. Presentations and demonstrations were given that describe how Synopsys' production-proven solutions predict the parasitics-related issues where design meets silicon and verifies, before fabrication, that your mixed-signal chips work.

IP and System-Level Solutions
At DAC, Synopsys showcased the breadth and depth of its DesignWare® connectivity IP portfolio as well as its commitment to IP quality. The five IP sessions focused on a range of products that included digital cores, verification IP, PHYs and high-speed Datapath components. In addition to the demos, Synopsys' expertise was also evident on two DAC panels: "Wireless USB – the Next Ubiquitous Connectivity Standard?" and "Developing Consumer SoCs—IP and Automation or Sticks and Duct Tape?"

Synopsys also demonstrated its latest System-Level Solutions, aimed at connecting hardware and software development flows for leading SoC platforms. Uniquely, Synopsys provides the only comprehensive system-validation solution, including models, tools, services, and links to HW verification. DesignWare Virtual Platforms enable concurrent HW/SW development, integration and validation, with significant time-to-market benefits, including the potential to shorten the design cycle by nine to 12 months. DesignWare Virtual Platforms are for software development and provide the fastest and most complete models of complex mobile platforms including TI OMAP3, Freescale MXC and Intel XScale, which allow complete system simulations to be run at 50 MIPS. Virtual Platforms represent the fastest growing segment in ESL, and have seen rapid adoption, making it the long-awaited killer application for ESL.

Professional Services
Synopsys' Professional Services group featured the Pilot Design Environment, which enables predictable tapeouts at 65nm. Synopsys consultants highlighted services that are available to help customers be more productive with their design transitions such as 90nm to 65nm, and ASIC to COT.

Partner Booth
The Partner Booth gave DAC visitors the chance to see the Synopsys IC design ecosystem with real solutions in action. Featuring technology from ARM, TSMC and Synopsys, the solution-oriented demo stations focused on ESL, low power, integrating design and process, and physical verification. Partnership was a strong theme throughout the show with leading customers and partners featuring in many of the Synopsys announcements, panel discussions and suite presentations.

Interoperability Breakfast Event
Dr. Chi-Foon Chan, President and Chief Operating Officer of Synopsys, hosted Synopsys' interoperability breakfast sponsored by AMD and HP. An audience of more than 150 heard industry veterans discuss the benefits and challenges of enabling interoperability for custom design through OpenAccess. At the event, the sixth annual Tenzing Norgay Interoperability Achievement Award was presented to Electronic Tools Company (also known as E-Tools), a leader in EDA data interchange tools and services, for its key contributions to the parser for the open source Liberty™ library format. The Liberty parser developed by Electronic Tools Company is currently in use by more than 50 EDA companies and 100 end-user companies.

DAC 2006, the showcase event for the EDA industry, saw Synopsys announce innovative DFM technology in PrimeYield, PrimeTime VX and Star-RCXT VX variation-aware design products. With a strong focus on faster verification with SystemVerilog, Synopsys presence in panel and technical sessions was underpinned by real-world technical demonstrations in the booth and suites.

The combination of proven innovative technology and expertise focused on achieving productivity and performance, are the key ingredients to enabling predictable success.

©2010 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.

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