| Technology Update|
Design Compiler® Topographical Technology: Enhancing Synthesis Predictability and Productivity
Priti Vijayvargiya, product marketing manager, Synopsys, explains how Design Compiler Ultra with topographical technology, eliminates costly iterations between synthesis and layout by accurately predicting post-layout timing area and power with testability, enabling faster time to results.
Topographical technology, the latest innovation in synthesis, delivers accurate correlation to post-layout timing, area and power, without wireload models. It is designed for RTL designers and requires no physical design expertise or changes to the synthesis use model. The accurate prediction of layout timing, area, testability and power in Synopsys' Design Compiler Ultra enables RTL designers to fix real design issues while still in synthesis and generate a better start point for physical design. Synopsys' Galaxy Design Platform also incorporates topographical technology within the physical design tools ensuring a smooth, convergent path from RTL to GDSII.
Replacing Wireload Models
Larger synthesis block sizes coupled with shrinking geometries have driven net delays to become the dominant delay in a path. When the average block size was in the 10K to 50K gate region, it was easier to predict net capacitances based on statistical information because the block sizes were small and the lengths of nets were relatively short. Wireload models (WLMs), with an estimated average net capacitance based on fan-out, were commonly used.
With synthesis block sizes now in the hundreds of thousands or millions of gates, it is much harder to estimate the net capacitances based on statistical information. This results in timing and area correlation issues where the results after RTL synthesis do not correlate to post-physical implementation results. The physical design challenge is amplified even further since place and route solutions cannot compensate for a bad start point handed off from synthesis.
Accurate and consistent timing, area and power estimates from the RTL design process are more critical than ever with the transition to larger and more complex designs. Predicted outcomes that correlate poorly with the physical design can lead to an increase in design iterations with an adverse impact on the project timescales.
Estimation based synthesis that is overly optimistic usually leads to a physical design that will not meet the required performance in terms of timing or the power budget. Usually the only course of action is to return to the RTL design, fix the design issues and then re-synthesize.
If the design team tries to anticipate an overly-optimistic estimate by overconstraining the timing in the first place, the synthesis process will respond by picking cells that are larger than necessary. This produces an area penalty that cannot be recovered in layout, and again, a complete synthesis iteration will be required to fix the problem.
How it Works
Topographical technology in Design Compiler Ultra utilizes Synopsys' best-in-class physical implementation technologies to drive accurate timing prediction within the synthesis engine, ensuring significantly better correlation to the final physical design.
Topographical technology drives synthesis with virtual layout-based timing which eliminates the need for users to provide WLMs for synthesis. With knowledge of the actual topography of the design, topographical technology accurately predicts net capacitances and continuously updates their values as the synthesis progresses. As an integral part of Design Compiler Ultra, topographical technology drives synthesis with accuracy for all design objectives including timing, area, power and test. In addition, topographical technology incorporates virtual clock-tree synthesis technology for accurate prediction of power - both leakage and dynamic power - post clock-tree synthesis. With topographical technology, RTL designers can focus on the real design issues while still in the synthesis phase thus, achieving higher productivity. Topographical technology requires no physical expertise or change to the current synthesis use model. Hence it is easy to adopt. In addition, it shares technology with Synopsys' physical implementation tool ensuring a convergent smooth flow from RTL to GDSII.
Minimizes Congestion and Improved Routability of Scan Chains
Traditional scan ordering in synthesis is based on alphanumeric instance names. This requires reordering of scan chains during layout to minimize scan wire-length and prevent routing congestion. However, this can adversely affect correlation between synthesis and post-layout timing, power and area data, especially when more complex DFT logic is used for scan compression circuitry.
Topographical technology uses virtual layout information to drive the original scan chain ordering in Design Compiler Ultra, which minimizes any re-ordering that is necessary, hence preserving correlation. Basic scan, multi-mode scan and Synopsys DFT MAX adaptive scan are all supported.
Tighter Integration with Floorplanning
A further enhancement that improves synthesis correlation is the ability to read a number of physical constraints from a design floorplan. These include information about the core area, the port locations, macro locations and even placement keepouts. This information is optional and needed only when working with a tough floorplan with lots of macros. Access to this information can further tighten the timing, power, test and area, correlation.
Galaxy Design Platform
The Galaxy Design Platform is an open, integrated design implementation platform with best-in-class tools, enabling advanced IC design. Anchored by Synopsys' industry-leading IC implementation tools and the open Milkyway database, the Galaxy Design Platform incorporates consistent timing, signal integrity (SI) analysis, common libraries, delay calculation, and constraints from RTL all the way to silicon.
Figure 1. Galaxy Design Platform
Topographical technology benefits both the front-end and back-end design teams. The RTL designer can be confident that the design that is handed off to the physical design team will meet the timing, area and power specifications when taken through to layout. Furthermore, any issues flagged up to the back-end designers are likely to be real issues that require special attention. For the back-end team, they will be starting the physical design with a high-quality netlist that will enable a smooth process to layout.
In addition to topographical technology, DC Ultra includes a comprehensive set of advanced features to deliver best synthesis quality of results for a wide variety of designs. These include advanced timing and area optimizations, innovative datapath optimization algorithms, powerful critical path synthesis, finite state machine extraction and optimization, and the ability to move registers through combinational logic to improve timing (register retiming).
Since its introduction, topographical technology has been proven across many advanced designs. Analysis of the benchmark data across a range of designs has demonstrated the superior correlation for timing, area and power. Figure 2 compares timing, area and power correlation between synthesis results and the design post-layout with DC Ultra topographical technology. Topographical technology shows improved correlation consistently across many designs.
A data point on the line denotes exact correlation.
Figure 2. Design Compiler Ultra Correlation to Post Layout Timing, Area and Power
We believe Design Compiler's topographical technology is a better approach to synthesis, generating results that more closely correlate to physical implementation and therefore reduce iterations between synthesis and physical tools. The topographical technology fits readily into our design flow, delivering area and timing correlation which is within three to six percent of post-placement results. In addition, with this technology we are realizing reduced congestion. These results, complemented by the improvements we have seen in DC Ultra 2005.09, are driving our decision to deploy this technology on our next-generation designs.
Dan Smith, director of hardware engineering at NVIDIA
ARM partners are continuously seeking ways to increase productivity. Utilizing Synopsys' topographical technology equates to a significant boost in productivity. The results generated by Design Compiler topographical technology have consistently correlated within 5% of post-layout timing and area on multiple cores. And, because Design Compiler topographical technology is part of the Galaxy Design Platform, it was very easy to integrate into our reference flow.
We have found the topographical technology to be very effective in delivering predictable flows. Using topographical technology our RTL designers were able to identify the design issues and fix them prior to physical implementation. The accuracy and predictability of results combined with the advanced optimizations of Design Compiler technology are what our RTL designers need for synthesis at 90-nm technology.
Gary Benzschawel, design manager at SGI
Topographical technology is a key feature of DC Ultra that enhances productivity for both front-end and back-end design teams. In addition it reduces the need for over-constraining designs in synthesis, improving quality of results further. Design Compiler's topographical technology accurately predicts post-layout timing, power, and area in synthesis with testability, eliminating costly iterations between synthesis and layout and enabling faster time-to-market. Topographical technology gives RTL designers early visibility into post-layout design issues, which allows them to be addressed while still in synthesis. It utilizes Synopsys' best-in-class physical implementation technologies to drive accurate timing and area prediction within the synthesis engine. As a result, RTL designers can generate a better start point for physical design to significantly reduce design time.
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