Innovative Ideas for Predictable Success
      Volume 1, Issue 4


  Technology Update
Spotlight Improving Physical Design with IC Compiler
IC Compiler is a critical part of the Synopsys Galaxy Design Platform, a key element enabling designers to achieve their performance and productivity targets in physical design, while supporting a predictable path to design closure. Saleem Haider, Senior Director of Marketing for Physical Design, Synopsys, explains why customers are transitioning to IC Compiler to implement designs across all process technologies.

IC Compiler is Synopsys’ next-generation place-and-route solution. IC Compiler unifies physical synthesis, clock tree synthesis, routing, yield optimization, and sign-off correlation to deliver unmatched design performance and designer productivity. These benefits improve turnaround time for designers working across all process nodes – mainstream designs as well as the latest technologies.

Figure 1. Design Compiler and IC Compiler duo form industry-leading implementation solution from RTL to GDSII

Differentiation for Complete Place-and-Route
Synopsys developed IC Compiler to address technology needs, such as power, yield and multi-mode design that were not considered when most of the current tools were architected back in the late 90’s. IC Compiler is a complete place-and-route solution including floorplanning, power, test, timing and signal integrity (SI) capabilities. In particular IC Compiler includes new technologies that are unique and make it a fundamentally different and better next-generation solution for physical design. These differentiators can be summarized as: Extended Physical Synthesis (XPS), Signoff-Driven Design Closure, and Yield Driven Design.

Extended Physical Synthesis (XPS): The EDA industry is very familiar with the highly successful Physical Synthesis technology introduced by Synopsys in the late 90’s. What made Physical Synthesis unique and powerful was that it brought together two technologies – synthesis and placement – that had traditionally been performed in separate steps and in separate tools. With XPS, IC Compiler extends that same concept of concurrency to the full place-and-route flow. Rather than treating placement, clock tree synthesis (CTS), and routing as three distinct steps, IC Compiler creates a unified optimization environment that concurrently addresses all phases. For example: XPS allows IC Compiler’s CTS engine to completely re-synthesize and replace the power gates in the clock, based on actual placement, timing, global routing and power data. This optimization is performed automatically during the construction of the clock and concurrently optimizes not only skew, but also power, congestion and the timing of enable signals. These optimizations are traditionally performed in three distinct phases (logical clock gating, followed by placement, followed by CTS), often by different tools. XPS allows IC Compiler to optimize the entire problem concurrently. The result is a more efficient low-power solution, which is generated in less time. XPS provides many more similar benefits by allowing the placement tool to determine routing layers for critical nets and enabling the router to alter cell placement. XPS breaks down the walls that have traditionally separated the different phases in physical design.

Signoff-Driven Design Closure: Layout designers are familiar with the frustration and delays caused when the results of the layout process do not match golden signoff timing. This problem is becoming particularly acute for designs with several operating modes and multiple operating conditions (corners) with the total number of mode/corner combinations becoming prohibitive.

Traditional approaches like sequential optimization or the creation of a single superset mode/corner suffer from either convergence problems (ping-pong effect) or unacceptable quality of results. IC Compiler’s signoff-driven timing closure methodology provides two major new technologies to addresses these issues. The first is to use golden signoff extraction and timing (Star-RCXT and PrimeTime-SI) data to directly drive the final timing closure optimizations in layout. This is accomplished by IC Compiler calling PrimeTime-SI and Star-RCXT incrementally (for speed) and using the golden results to automatically perform incremental timing optimizations in the layout. IC Compiler’s second technology leap is to optimize all modes and corners concurrently. All modes and corners are timed simultaneously, and the timer operates on the worst violations across all modes/corners. The benefits of this two-pronged approach are better quality-of-results, more efficient timing closure and a much faster time-to-results.

Yield Driven Design: Advanced process technologies suffer from a growing list of yield-loss mechanisms that require the layout designer to carefully consider yield as an explicit design goal next to speed, power and size.

There are two reasons for this:
  • Feature sizes on silicon have shrunk to well below the wavelength of the light used to create them. This is why layout has become more sensitive to yield loss.
  • Most yield optimization techniques have an impact on timing, power and/or area, and therefore need to be considered during the design stage, and not just postroute. IC Compiler was designed to respond to these challenges with a sophisticated array of yield analysis and optimization techniques, including critical area analysis, timing-driven wire spreading, timing-driven metal fill and multipattern via doubling. This allows every designer to apply these foundry-validated optimizations and measure the results numerically.

The Benefits of IC Compiler
New technologies within IC Compiler provide advantages across the board. Benefits are significant in the areas of quality-of-results, turn-around time, simplicity of use and advanced features. These significant advantages have proved instrumental in moving companies such as ARM to provide support for IC Compiler in their Reference Methodology, for example.

Every design benefits from the typical 10% improvement in chip performance that XPS makes possible. For designs where additional performance is not needed, this improvement can be traded for smaller die size, lower power and higher DFY application. The streamlined architecture also delivers faster runtimes and, more importantly, faster convergence to a signoff-correct result.

IC Compiler’s faster overall convergence – as opposed to simple runtime - is made possible by its new timing architecture that uses exactly the same timing engine from synthesis (Design Compiler) all the way to GDSII tapeout. For advanced designs implementing multiple modes and corners, the concurrent optimization in IC Compiler is much faster than sequential optimization and avoids the ‘ping-pong effect’ between modes. IC Compiler also offers a simpler and more elegant user interface based entirely on Tcl. There are only three core commands with options, and these suffice for the majority of designs. Lower level atomic commands are available for precise control.

Extensive floorplanning features are included as an integral part of IC Compiler which simplifies hierarchical design and the creation of block timing models (ILM) for SoC integration.

Beyond these benefits for mainstream designs, IC Compiler also offers a range of advanced features that are of interest to more advanced design styles. There is a complete low-power flow including clock power gating, multi-threshold libraries and multi-voltage support. Test is also comprehensively supported with scan chain re-ordering and adaptive scan techniques.

IC Compiler Usage
IC Compiler is in active use across a broad range of applications and silicon technologies. IC designers from all major technology regions have been deploying IC Compiler into production to leverage the benefits of XPS, signoff driven closure and enhanced support for DFY. Many of these customers have shared their experiences at Synopsys user’s group meetings and at the Design Automation Conference. Some results from customer designs are shown below.

Figure 2. Predictable correlation between post-synthesis and post-layout results for area and performance

Figure 3. IC Compiler consistently improves performance (MHz)

Figure 4. IC Compiler consistently reduces leakage power

Figure 5. IC Compiler accelerates turnaround time, on average 2x faster across a range of designs

Continued customer adoption of IC Compiler is being driven by the ability of designers to achieve better results in complete place-and-route across both mainstream and advanced designs. Design teams have achieved better results in terms of timing, power and area, and improved productivity through consistently faster turn around time. Furthermore, superior ease of use ensures that IC Compiler can be rapidly incorporated into existing Synopsys design flows.

©2010 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.

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About Saleem Haider
Saleem Haider is Senior Director of Marketing for Physical Design at Synopsys.


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"IC Compiler is a complete place-and-route solution including floorplanning, power, test, timing and signal integrity (SI) capabilities."