| Technology Update|
A Practical Methodology Calculates IR Drop Targets for SoCs
The shift to smaller process geometries has led to a dramatic increase in problems due to IR drop. Michael Solka and Jonathan Young, both with Synopsys Professional Services, explain how the right IR drop target should be found before steps are taken to address the problem.
Based on fundamental information about the physical environment of the SoC in the system, manufacturing tolerances, and the basic application of Ohm’s Law, straightforward calculations can give appropriate targets for IR drop on the SoC’s power grid. Without these calculated target values, design engineers typically rely on old rule-of-thumb targets that do not apply in today’s smaller process geometries. Unfortunately, the timing effects of IR drop may not be seen until the prototype is characterized in the laboratory, which is certainly too late.
IR drop can cause major timing problems. There is extensive information available on how to minimize the drop with good power planning techniques. There is also good information available about detecting problems with static timing analysis (STA) tools, such as Synopsys’ PrimeTime SI. However, there is a scarcity of information on how to set the right target IR drop in the first place.
This article seeks to close that gap with an analysis of IR drop components and a methodology for determining realistic IR drop targets. Much of the value in setting a target depends on when the target is set in the design process. This article cannot prescribe exactly when the target should be set, since various data values used in the proposed methodology become available at different times for different projects. However, the earlier the physical implementation team can get a good target value for IR drop, the better the team can design a robust power distribution network. Like most design specifications, the final target is often determined in an iterative fashion as the implementation team examines the tradeoffs.
The easiest way to grasp the methodology for determining IR drop targets is through a practical example, so the explanation that follows shows the calculations for a typical 130nm SoC. Before working through these calculations, though, consider the dual nature of the IR drop problem for SoCs.
IR drop affects cell performance and characterization
As the term implies, IR drop is a decrease in voltage that results from the current and resistance associated with the power network. This voltage drop leads to two types of problem. First, a reduced voltage difference between the VDD and VSS pins of a standard cell will reduce the cell’s operating performance. If the cell is on a critical path, the decrease in cell performance could reduce the chip’s operating frequency. The IR drop also reduces the cell’s noise immunity and in extreme cases can lead to functional failures. Smaller process geometries have led to a dramatic increase in such problems.
Because of the severity of these issues, STA is required to predict the problems. STA tools have gained a great deal of functionality for predicting the operational performance of a standard cell based on a case-by-case voltage level applied to the cell. However, most of the STA signoff process still assumes that all standard cells have the same max (VDD plus 10 percent minus 0V), nom (VDD minus 0V), and min voltages (VDD minus 10 percent minus 0V) applied to them. Note that these values allow VDD to vary by ±10 percent, but VSS is assumed to stay at 0V.
The second type of IR drop problem involves library characterization. The standard cells in a library are characterized to give accurate predictions of their real-world performance over specified ranges of voltage, temperature and silicon processing conditions. As process geometries have shrunk, the equations needed to keep the predicted performance correlated to the measured silicon have become more complex, and significant deviations now occur when a standard cell operates outside of its characterized range.
Therefore, when performing STA on a design using min conditions, it is important to ensure that the minimum voltage seen by a standard cell is within the library’s characterization conditions. Otherwise, STA cannot accurately predict the real-world silicon performance.
Sources of IR drop
As mentioned earlier, IR drop occurs mainly because of the resistance of the SoC power network combined with that network’s ability to source and sink current from the VDD and VSS pins. There are other potential causes for voltage loss in the SoC’s standard cells, however, and those causes involve the system in which the SoC operates.
Typically, an SoC interfaces with other devices on a PCB. The system’s power supply is also on the PCB or nearby and delivers power via a voltage regulator. A typical voltage regulator provides a voltage that is stable within 1.5 to 2 percent of its target output. The PCB’s power distribution network delivers this supply voltage to the SoC. Today’s high-speed, multilayer PCBs can show up to 18.5 mV of voltage drop from the voltage regulator to the furthest devices on the PCB, although a value between 11 and 14 mV is more typical.
Thus, the total IR drop includes the drops on both the board and SoC:
IRtotal = IRpcb + IRchip (1)
where IRpcb consists of IR drop associated with supplying the SoC with power, and IRchip consists of the IR drop on the SoC itself.
Calculating IR drop targets
To demonstrate a practical method for determining IR drop targets, the following calculation uses the example of a typical 130 nm SoC and a 1.2V power supply. The starting assumptions are thus:
- A standard cell library characterized to 1.2V +/- 10 percent
- A power supply on the PCB of 1.2V +/- 2 percent
- 18.5 mV of IR drop from the power supply to the SoC
Based on the standard cell characterization data, the SoC power network must maintain at least 1.08V (1.2V minus 10 percent) to all the standard cells. It can also be inferred from the starting assumptions that the worst-case voltage delivered from the power supply is 1.176V (1.2V minus 2 percent). Given these values, a target IR drop is easily determined by subtracting the voltage requirement from the voltage supplied:
IRtarget = Vsupply – Vrequire
= 1.176V – 1.08V
= 0.096V (96 mV)
Letting IRtarget be IRtotal in equation (1) and using the 18.5 mV IR drop assumed on the PCB gives a new target for the IR drop on the SoC:
IRchip = IRtarget – IRpcb (2)
= 96 mV – 18.5 mV
= 77.5 mV
Assuming an even split between VDD fall and VSS rise, an initial target for the power network design might be 38.75 mV on each of the VDD and VSS networks from the pins of the SoC to the standard cells. However, this target still presents a somewhat vague and potentially misleading requirement to the physical designer because the SoC’s package and die must share the specified drop. Consider a further refinement of the target:
IRchip = IRpackage + IRdie (3)
where IRpackage consists of IR drop within the package, and IRdie consists of IR drop on the die. The latter component can be further broken down as:
IRdie = IRpads + IRcore (4)
where IRpads consists of IR drop across the bond pads and the I/O cell, and IRcore consists of IR drop from the I/O cell to the furthest standard cell. Note that the location of the “furthest standard cell” depends on both floorplan considerations and circuit operation. Figure 1 shows the individual components of IRchip leading to IRcore for a wire-bonded chip. Flip-chip designs involve slightly different considerations (more on this later).
Figure 1. IR drop Across the Input Path to an SoC’s Power Network
Combining (3), (4), and the value for IRchip found in (2) provides a formula for determining an actionable IR drop target for the physical design process:
IRcore = 77.5 mV – IRpackage – IRpads (5)
To determine values for IRpackage and IRpads, consider that IRpackage consists of two components:
IRpackage = IRtrace + IRbondwire
where IRtrace is IR drop across the traces in the package, and IRbondwire is IR drop across the bond wire. Values for these parameters vary greatly depending on package type, the number of package pins dedicated to VDD and VSS, and the total power dissipation of the device. As a result, it is necessary to consult package vendors when performing these calculations for an SoC project. For illustrative purposes, the calculations that follow assume 10 mV for IRpackage.
IRpads can be calculated based on the resistance of the wires in the I/O cell, as provided by the I/O cell vendor or extracted during the design process. Multiply the resistance by the current that the cell is expected to carry. There is a choice of two alternatives for this current:
- Absolute worst case based on the cell design and current-carrying limits inherent to the technology
- Expected worst case based on the expected power dissipation of the SoC and the number of VDD (or VSS) cells in the SoC
The choice depends on the desired margin and the accuracy of the expected power dissipation of the SoC. Again, the following calculations assume 10 mV for IRpads.
Substituting the calculated and assumed values into (5) gives:
IRcore = 77.5 mV – 10 mV – 10 mV
= 57.5 mV
Finally, evenly splitting this value between the allowable VDD fall and VSS rise gives a target IR drop of 28.75 mV for each network from the I/O cell to the furthest standard cell. The split does not have to be perfectly even, of course, so long as the total drop between the two supply rails does not exceed the target.
Example IR drop values
Figure 2 shows how IR drop values change for different process technologies when calculations and assumptions are used that are similar to the example earlier in the article. The impact of lower core voltages at smaller process geometries is clearly seen.
Figure 2. Calculated IR Drop Target Values for Different Processes
As shown in Figure 3, the values for flip-chip designs differ slightly from the wire-bond values shown elsewhere in this article. The main differences lie in the assumptions for the calculations of IRpackage and IRpads. Because flip-chip designs have no bond wires, IRpackage equals the IR drop in the package lead frame. In the case of IRpads, flip-chip designs typically have an array of VDD and VSS bump locations across the core area of the die, so very little IR drop occurs in the pad cell.
As described earlier, many variables associated with the calculation of these parameters depend on the particular details of each chip. For illustrative purposes, Figure 3 assumes IRpackage and IRpads values of 3 and 1 mV, respectively.
Figure 3. Calculated IR Drop Target for Flip-Chip Packages
One of the benefits of moving to a flip-chip design approach is that the allowable IR drop budget increases. Additionally, the flip-chip design’s power grid is generally easier to design because the distance from the VDD and VSS bumps to the “furthest standard cell” is typically less than the corresponding distance in a wire-bond device. Both of these flip-chip advantages come at the expense of a higher-cost packaging solution, so you have to examine the full set of tradeoffs.
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