been the leading provider of high reliability semiconductors that withstand the harshest of elements produced by space environments. Recently, they have developed an advanced 150-nanometer (nm) manufacturing process with inherent radiation-resistant characteristics based on Silicon-on-Insulator (SOI) technology. SOI provides significant benefits beyond superior resistance to radiation, such as improved performance and significantly lower power consumption. Gary Kirchner, Director of Engineering at Honeywell Solid State Electronics Center, describes the jointly-developed concept-to-parts solution for development of next generation rad-hard ASICs.
Honeywell and Synopsys: Concept-to-Parts
Solutions for Next Generation Rad-Hard
For many military and aerospace companies, closing the technology gap between the commercial and military aerospace worlds has become paramount for the development of next-generation applications such as satellites and space vehicles. Over the past two decades, Honeywell has
Today's military and space programmes demand high performance, highly integrated chips that are resistant to radiation and capable of sustaining performance, both during and after exposure to high doses of radiation. Historically, extreme radiation conditions have required mature microelectronic process technologies. This has hampered military and aerospace system designers from taking advantage of the most progressive technologies and silicon manufacturing processes available to commercial colleagues.
Next-Generation Rad-Hardened ICs
An agreement between Synopsys and Honeywell Solid State Electronics Center (SSEC) now provides an industry-leading design and manufacturing infrastructure for components that require radiation-hardened (rad-hard) and radiation-tolerant functionality. The Department of Defense (DOD) Radiation Hardened Microelectronics Accelerated Technology Development programme has provided funding to Honeywell, the world's number one producer of rad-hardened ASICs, for development of a deep submicron multi-million gate ASIC design and fabrication capability.
This collaboration enables multi-million gate ASIC applications, with levels of integration previously seen only in applications without radiation performance requirements. These new techniques deliver significantly enhanced data computing and speed to chips and other components used in aircraft, satellites and space vehicles. It will also provide enhanced design predictability, using a proven design flow based on Synopsys' Galaxy™ Design and Discovery™ Verification platforms that has been tailored to Honeywell's 150-nm process technology.
The new, integrated design flow combines Very Deep Submicron Design (VDSM) electronic design automation (EDA) tools and infrastructure with state-of-the-art SOI fabrication to address requirements of next-generation military and aerospace chips. The solution is architected to support ASICs with gate usage counts of around 15 million and core speeds greater than 500 MHz.
Advantages of Radiation-Hardened SOI CMOS Technology
Non-hardened commercial ICs exhibit errors and reliability problems when exposed to radiation environments. Increasingly sensitive to errors caused by protons, neutrons and high-energy particles, even natural radiation levels experienced at the high atmospheric altitudes flown by commercial aircraft can induce failures (such as soft errors) in state-of-the-art commercial CMOS ICs. Therefore both civilian and military aerospace applications require either rad-tolerant or fully rad-hardened devices.
Compared to bulk CMOS, 150-nm rad-hardened SOI CMOS offers significant cost and performance gains; 30 percent lower power consumption, 20 percent increased performance, 15 percent higher density and 4-6 dB lower crosstalk. In addition, high-performance passive devices can be fabricated, which are capable of supporting advanced mixed-mode design.
These advantages have propelled SOI into extremely high-performance commercial applications. For radiation sensitive applications, SOI offers the most cost-effective fabrication technology available.
Because the wells in an SOI device are completely oxide isolated, the parasitic condition that causes latchup in CMOS devices is eradicated, reducing design risk and testing effort. In addition, buried oxide and trench isolation hardening eliminates the risk of trapped gamma rays changing the device's threshold voltage.
Figure 1: The SOI Process Eliminates Latchup
The SOI's charge collection volume is 10 times less than that of bulk silicon, which removes the need for resistors or high-drive transistors to maintain logic state. This inherent advantage is then further enhanced using body ties that ground ions, with less than a 10 percent penalty.
Radiation resistance can be further enhanced by applying several types of device hardening. Key cells in the SIC library can include specialist structures that introduce delays in preventing the circuit switching state before ion charges recombine. If these structures are built into the ASIC library, no intervention by designers is necessary.
Honeywell’s family of ASIC technologies is designed to meet total dose requirements up to 1000 Krad (Si) and <1E-11 upsets / bit-day for Single Event Upset (SEU).
Figure 2: Design Flow Hardening Techniques
Very Deep Submicron Design Considerations
Moving to an ASIC technology that provides the 15-million gate densities made possible by 150-nm SOI requires a new set of design techniques. Designers must now consider VDSM physical effects and the design productivity issues associated with creating enormously complex ASICs within a reasonable time frame.
A VDSM-optimized design flow requires physical design steps that ensure logic timing accounts for the interconnect delay required for interdependent logical and physical design and manufacturing. It is essential that timing, power and signal integrity closure is achieved efficiently.
Hierarchical design enables the effective management of large gate counts. By dividing a design into multiple blocks, designers can work on blocks separately and in parallel from RTL through to physical implementation. This keeps tool runtimes short and makes block-level closure timing relatively easy to achieve. On completion, blocks are integrated to create the final chip implementation and modeled as black boxes.
IP core use has become common in advanced ASICs, since VDSM densities make it prohibitive to design each ASIC transistor from scratch. Hierarchical design can accommodate 'off-the-shelf' or application-specific IP cores designed by an in-house team. The ability to use complex and proven IP, from high-performance processors and standard interface controllers to mixed-signal functions such as A/D converters and phase-locked loops, is critical to the design of 150-nm SOI ASICs.
A Contemporary Design Infrastructure
With the level of device densities that are possible with Honeywell’s 150-nm process technology, the infrastructure for effectively managing people, data, and hardware and software resources is critical to project success. Often design teams and resources are distributed amongst multiple sites, an outgrowth of the increased complexity and breadth of skills required for today’s ASIC developments. During critical stages of the design, peak compute requirements often introduce bottlenecks.
To maximize design productivity, Honeywell and Synopsys have established the Design Collaboration Environment (DCE), an Internet-accessible, highly secure environment that provides on-demand access to design tools along with extensive compute and storage capacity. The DCE enables real-time sharing of design data for engineers at multiple remote locations – including those of Honeywell, Synopsys and our mutual customers as needed – to act together as a single design team with a unified design database and flow, applying the best expertise regardless of geography or time zone.
The DCE makes it possible to work with both Honeywell and Synopsys in a development model that is far more flexible than traditional ASIC options. The model includes available design services from Synopsys Professional Services that may include the design of some or all of the ASIC. These design services can begin with a design handoff at the specification, RTL or netlist stages, or as a fully collaborative effort with our customer throughout the development process.
The design flow, also accessible through the DCE, is also optimized for the Honeywell 150-nm process technology. The Honeywell-Synopsys design flow utilizes a validated sequence of tools and associated scripts from Synopsys’ Galaxy Design and Discovery Verification platforms. The flow includes procedures and tools to support radiation performance, including rad-hard-level attribute-based synthesis. Other examples include signal and cell EM analysis and rad-hard power plan methods. The design flow also supports packaging and testing technologies important for the reliability and electrical performance requirements of mil/aero applications such as flip-chip packaging, memory and logic Built-in Self Test (BIST) and scan/ATPG based testing.
Packaging and Test
To match the advanced performance of the chips, Honeywell has established a back-end packaging and test model equally as progressive and efficient.
The packaging of space electronics affects the integrity of a chip’s I/O signals (through interference inductance) as well as a chip’s overall ability to resist radiation. Military ASICs have traditionally been packaged in a hermetically sealed, wire-bond-style package with up to 300 unique signal I/Os. Some wire-bond styles can be enhanced to improve performance in the 7- or 8-million-gate range, but it is not an efficient answer for deep-submicron, multimillion-gate ASICs.
The optimal package alternative for next-generation mil/aero ASICs is the flip-chip packaging style, a commercial packaging technology that can meet mil/aero requirements for electrical performance, I/O count and other considerations for VDSM, high-gate-count ASICs. The package supports as many as 1000 signal I/Os, increases connection speed, keeps more heat away from the chip, and provides radiation advantages (i.e., dose rate upset).
Testing of 150-nm mil/aero ASICs also requires leveraging commercial tools and practices while accommodating the stringent reliability requirements of mil/aero applications. Advanced tools allow for scan insertion and memory BIST to address manufacturability requirements and ensure reliability. Logic BIST is commercially available for in-system testing and combines with memory BIST to allow customers to verify device functionality. These methods allow thorough testing and screening of parts during burn-in, AD/DC parametric testing, functional testing and automatic scan testing. Using industry-standard formats for test vectors enables efficient hand-off from ASIC developers to manufacturing test.
Industry Leading Rad-Hard Technology
By coupling an advanced semiconductor fabrication process with hardened standard cell libraries, the latest packaging and test technologies, a full range of standard IP cores and a highly automated design flow, rad-hard ASICs offering performance comparable to commercial grade parts can be produced.
Honeywell and Synopsys have created a 150-nm ASIC design and manufacturing flow based on Synopsys’ Galaxy Design and Discovery Verification platforms and Honeywell’s 150-nm SOI process, which leverages proven commercial technologies to enable a fast, more predictable path to rad-hard and rad-tolerant ASICs.
Gary Kirchner, Director of Engineering and Technology, Honeywell Defense & Space Electronic Systems, is the engineering leader at Honeywell's Solid State Electronics Center responsible for design, development and production of avionics, controls and rad-hard electronics for various space platforms. Honeywell currently is one of the world-leading rad-hard ASIC and Memory product providers for the U.S. Department of Defense. Kirchner, considered foremost industry expert in rad-hard CMOS electronics, will be leading successful development of 150 nanometer technology, S150, and production through Honeywell's new rad-hard fab slated for finalization in early 2005.
Kirchner has been with Honeywell since 1976 has held various engineering and management positions throughout the organization. During his tenure, he has earned several prestigious awards, including Honeywell's top technical and management award as well as selected as a Malcom Baldrige finalist. Kirchner holds a Master's and Bachelor's degree in Electrical Engineering from the University of Minnesota, and is an active member of IEEE and ASQC.
Honeywell International is a $22 billion diversified technology and manufacturing leader, serving customers worldwide with aerospace products and services; control technologies for buildings, homes and industry; automotive products; turbochargers; specialty chemicals; fibers; and electronic and advanced materials.
Honeywell is under contract with the U.S. Department of Defense for the Radiation Hardened Microelectronics Accelerated Technology Development Program (Defense Threat Reduction Agency sponsored contract DTRA01-03-D-0018-0001 and AFRL Agreement F33615-02-9-5325)
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