Technology and Productivity Momentum
Part 2. Dr. Aart de Geus, Chairman and Chief Executive Officer of Synopsys, provides an overview of the recent Synopsys product roadmap, highlighting the key technology advances within the Synopsys flow that are enabling productive design and verification. Part 1 of this article can be read here.
The Next Wave: DFM and IP Reuse
The industry context (Part 1) provides the basis for the strategy we have pursued over the past ten years. This strategy has been to ensure that we have completeness in all the technology that is required to tackle complex chip design. Execution of this strategy began with synthesis implementation, and gradually filled out all the steps to go from RTL to tapeout. In parallel to this, we developed and acquired the elements of a verification flow to span all the way from system-level down to analog mixed-signal and transistor-level verification.
As we move to smaller geometries, it becomes necessary to focus on design for manufacturing (DFM). Fundamentally this means connecting to the physics of what actually happens on the chip. Unless we connect the DFM information directly in the implementation tools, over time, we will not be able to achieve good yield.
At the same time, because so much more functionality can now be integrated on a chip, it is clear that to design ICs from scratch is not a recipe for success. Systematic IP reuse is an important and growing factor in design. Using pre-designed blocks of IP considerably improves design productivity, however the quality of the IP is key and implementing comprehensive verification methodology for the IP is extremely important. Increasingly we must consider IP reuse and verification together.
Correlation Enables Systemic Solutions
Within both Synopsys’ implementation and verification platforms, Galaxy and Discovery, significant advances have been made to solve many interdependent problems simultaneously. This concurrent approach is based on enabling accurate correlation between multiple tools.
The implementation platform has been significantly simplified over the past year. The verification platform now spans system design, RTL, right down to detailed transistor design. The implementation and verification IP portfolios have been considerably expanded. New DFM products cover photolithography, physical verification, all the way to TCAD, where we have the capability to simulate transistors literally layers of atoms at a time. Professional services support the entire portfolio.
It’s a fact of life that flows which contain best-in-class tools may not yield best-in-class results. Fragmented “Frankenstein flows” are actually very difficult to manage and achieve good results. We have moved towards more structure in flows. Central to this is the concept of correlation. As well as the requirement that all the issues such as SI, power and so on are addressed, all the tools must possess the same understanding of these optimization functions.
Early in the flow, we are interested in estimates of what will happen later in the design cycle. These estimates must monotonically improve in accuracy as the design is refined towards tape-out. In other words, ensuring that all of the products have the same understanding of the nature of the optimization is crucial. We refer to that as correlation within the flow. Achieving this level of correlation is a pre-requisite to the next step.
What we have been striving for is the ability to concurrently optimize for several different functions, in other words, trading off power vs. speed vs. yield, area and so on. It has taken the past three years and a significant amount of development effort to achieve, but that is what we have done. Enhanced productivity is what you get when you put it all together. In order to do this, first it is necessary to ensure all the parts are there.
Toward a Complete and Correlated Flow
For Synopsys, the Avant! merger was a big step, because it added a set of physical design tools to the product offering. Although the product portfolio was then reasonably complete, this was not sufficient, because the flow was neither complete nor correlated. Fixing the correlation problem by the use of common timing engines throughout the flow has been a significant development project, but this is now done and Synopsys can claim to have a complete and correlated flow.
This effort has been validated because we have seen an immediate improvement in overall productivity, according to many Synopsys customers, with the most recent product releases.
Synopsys also continues to invest in the next generation with products such as IC Compiler, which takes a number of what were distinct tasks and integrates them in a much closer fashion. IC Compiler is a major step forward in providing enhanced productivity. The first thing that IC Compiler users reported was a 40 percent improvement in time-to-results. That’s a big step considering that this product takes many of the place and route steps and performs them in one flow, bringing a dramatic improvement in overall productivity. Additionally, users report an 8-10 percent improvement in quality-of-results, be that speed, area or power.
Finally, IC Compiler includes a large set of yield improvement capabilities. Overall, this is a major advance towards yield optimization. Inside, we have taken the placement, clock-tree synthesis and routing steps, and performed them simultaneously, while optimizing for each different factor. The typical problem encountered in the past is that convergence can suddenly become disrupted because of surprises with routing congestion, or with timing predictability as the clock tree is inserted. Often, this is the stage when schedule slips become very visible. We have focused on addressing this problem and added a new set of algorithms that have been able to combine these steps, and achieve reduced uncertainty within the flow.
In other words, the early expectations that have been set are met as accuracy is refined later in the flow. One of the key reasons we have been able to achieve this is that we have taken advantage of our product PrimeTime as a sign-off tool in enhancing the overall implementation flow. We have also put in place a discipline that allows us to measure timing correlation amongst the different tools in the flow. Considering, for example, the timing slack between place and route and PrimeTime, the signoff tool, there is a remarkably good alignment between the two. We have achieved much better alignment with the ‘reality line’ in recent releases, while deliberately erring on the side of pessimism.
Approaches to Optimizing for Yield
We have been increasingly successful in optimizing for yield. One patent-pending technique that we have implemented is based on wire spreading. Following a critical area analysis, which identifies those areas that are very tightly-packed and where a random event due to a particle defect could cause two lines to connect, the aim of the optimization is to spread the wires. Of course the spreading cannot be too great as the overall chip area must still be minimized, so local optimization is required. In addition, timing integrity must be retained as the wires are moved around. This example illustrates the challenge involved in trading off timing against yield and area, all at the same time.
Figure 1: The risk of defects affecting yield have been significantly decreased in the right hand figure, showing post-optimization critical area analysis
In order to be able to talk about yield improvements gained from a particular technique in a quantitative manner will require a number of test cases to be developed to demonstrate the improvements on yield, and continued to data gathering from known designs. For example, a customer recently reported a 4 percent yield improvement gained through another technique, which is the creation of timing-driven redundant vias within IC Compiler.
ARM is a leading IC Compiler customer that has reported benchmark data which substantiates the capabilities of the product. Benchmarking IC Compiler against their reference flow with the ARM926EJ-S core targeting a 130nm process, ARM first achieved a 40 percent faster turnaround time with comparable design performance. Subsequently ARM implemented a flow that gave 8 percent better performance in comparable turnaround time, and finally a flow that provided both superior performance and turnaround time. ARM also noted the superior predictability and correlation delivered by IC Compiler. These types of results are typical.
Although IC Compiler has been one of our major recent product introductions, it’s important to remember that its development has been enabled by investment to the overall product infrastructure, including correlation improvements, and the benefit of this will be realized in each subsequent product introduction.
Design Compiler® has also been updated to include a set of capabilities that enable the estimation of the effect that place and route will have on the design. This is done without the traditional wireload models, but instead using an understanding of what the place and route system will do through a technology called Topographical Synthesis. The results of this synthesis correlate extremely well to the place and route output. Specifically, with respect to timing the results are good, for area the correlation is excellent.
This approach again boosts RTL design productivity as having accurate information early in the design process enables the best decisions to be made with respect to the architecture design, and costly iterations between synthesis and place and route are also reduced.
Tapeout Physical Verification
The main characteristic of physical verification is that the amount of data that must be handled is mushrooming. The central challenge is that there is a lot of detailed verification to be done, which is quite complex and very context-sensitive, and can take an inordinate amount of compute resources. To combat this we have invested significantly in enabling Hercules, our physical verification product, to take advantage of distributed computing. Data distribution is possible on a layer-by-layer basis as well as across sub-portions of the design.
In general, we as a company will pay much more attention in the future to the relationship between Synopsys applications and the compute infrastructure. We have successfully worked with customers to tune their compute environment to the needs of the product, often with dramatic effect.
A recent customer-provided example of physical verification illustrated a runtime speedup from 43 hours to less than three hours achieved by adding fewer than 20 CPUs. Hercules is scalable to run on over 50 CPUs.
Besides an advanced distributed computing capability, we have invested in Hercules in other ways in order to improve the single CPU runtime, despite the physical verification tasks having increased in complexity. We have also improved the integration of Hercules with the DFM flow. This is an area that will grow in importance, with capabilities such as litho-aware routing planned for future versions.
Floorplanning with JupiterXT
The JupiterXT floorplanner has also seen significant enhancements over the past couple of years. Runtime has been improved, and the capacity of the product has been extended to be able to handle many more instances, since very often floorplanning is performed by using blocks at different levels. Automatic macro placement is a feature that has delivered real productivity value to many customers, while continuing to yield very good results.
Power distribution is a big issue in most ICs, and this needs to be understood at the floorplan level as it impacts many of the subsequent steps. All of the floorplanning activity is connected through the same database, coupling place and route with the synthesis process, ensuring correlation between these key steps.
We have also integrated a simplified version of part of the router within the floorplanner. This approach ensures that whatever the floorplanner does is not immediately undone by the place and route system. Again, monotonically decreasing uncertainty is the principle by which we are able to improve overall productivity and predictability.
Approach Substantiated by Advanced Tape-Outs
Because Synopsys is involved in some aspect of virtually every single advanced design, we can accurately report, in aggregate, the statistics of the leading-edge designs. We believe there have been around 500 active 90nm designs to date, with 220 tape-outs. Of those, the vast majority have used a Synopsys flow for the back-end physical design.
At 65nm, there are fewer active designs and around 20 tape-outs. Again, the majority of 65nm designs have been designed with Synopsys tools. Our overall impression is that design in general at 90nm is progressing well, and 65nm feels like a continuation of the key 90nm issues. At 45nm, however, we expect a significant discontinuity in complexity and a whole raft of new deep-yield issues to emerge.
Verification: New Technologies
While the state space for verification has grown dramatically, Synopsys has invested massively in verification solutions. This has enabled the delivery of faster and faster simulation, and also development of all the other capabilities that are needed.
Our verification strategy has delivered many new technologies over the recent years. A few years ago simulation was the core of what verification was about, and simulator performance was everything. Today, a faster simulator is still of very real benefit. But as we moved towards more sophisticated chips it became clear that verification was much more than simulation.
The creation and management of good testbenches was an essential step forward in verification methodology. Good testbenches have to be measured against the coverage that can be achieved. Assertions and directives can simplify testbench design, so much so that specialist languages have evolved to support their use. As this technology was emerging, our aim was to be able to bring everything together within a single environment, a single language and a single compiler to combine assertions, testbenches and simulation at the most important points in the flow.
As well as a high degree of emphasis on core simulation performance, we have also developed technology for bug-finding techniques, especially difficult to find bugs which may be buried very deep in the state space.
Today, VCS®, which was originally just a simulator, now has a broad set of capabilities which are constantly evolving. As well as investment in formal verification technologies, we have also developed mixed-signal verification, and verification IP. VCS offers the capability to address both the simulation and the testbenches within a single compiler. This approach typically offers a 5X improvement in performance, which has been substantiated by many customer benchmarks.
Looking forward, it is clear that verification will continue to grow as an important field. The overall management of the verification process, on multiple sites and different compute environments, will become increasingly important. This is an aspect of verification we will continue to focus on.
SystemVerilog combines the ability to use testbenches and assertions within a single language which is aimed at enhancing the efficiency of design and verification capture, and simulation productivity. SystemVerilog has gained momentum, with leading design teams adopting the language to tackle the most complex design and verification problems.
The Verification Methodology Manual, jointly authored by ARM and Synopsys, is centered on the use of SystemVerilog. Synopsys’ Pioneer-NTB testbench automation tool enables SystemVerilog interoperability with other simulators, including non-Synopsys products, and opens up access to the advanced features provided by SystemVerilog within a Synopsys environment including advanced features for debug and testbench manipulation. In summary, Synopsys provides everything required to design in SystemVerilog, all available today.
IP for Implementation and Verification
Reuse of IP is fundamental to improving design and verification productivity. It is actually non-trivial to design IP for reuse, and low quality IP can hurt rather than help design productivity. Synopsys has a long history in developing IP for re-use and we have built on our experience and understanding of the needs around quality and reusability in order to introduce literally hundreds of building blocks for both implementation and verification over the past several years. Bringing this right up to date, recent introductions have included four new interface IPs, including a Certified Wireless USB Device Controller; Mixed Signal IP (PHYs) for the PCI Express, SATA & XAUI protocols requiring only 30-50% of the power consumption compared to other solutions in the market; AMBA™ 3 AXI™ Synthesizable IP which enables designers to easily adopt the AMBA 3 AXI protocol; and the VCS Verification Library which allows designers to achieve up to five times verification performance improvement when used with Synopsys' VCS RTL verification solution, or Pioneer-NTB SystemVerilog testbench automation tool.
Synopsys Professional Services
Through more than 10 years of working with our customers on their most challenging chip designs, Synopsys Professional Services has built a leading-edge design competency and infrastructure, with consultants skilled in the latest EDA technology and design practices. And we bring that knowledge and expertise to each and every customer engagement, identifying then resolving the design bottlenecks that pose the greatest risks to your project, providing support all the way through tapeout. Whether you need to outsource the entire chip design or augment your team with on-site design assistance - or a combination of the two - Synopsys Professional Services offers flexible engagement models that best address your design goals.
The inseparability of advanced technology development and economic globalization will continue to drive the delivery of exciting new electronic products. Against a backdrop of higher semiconductor volumes and lower product costs, design teams will be increasingly faced with more complex design issues to solve, in order to realize those products.
The interdependency of many of the new design issues for 90nm and 65nm geometries means that they must be addressed concurrently, such that variables are optimized together, if design convergence is to be achieved. This approach requires tools that are accurately correlated within an integrated and complete flow.
Synopsys has invested considerably in building technology to support a complete and correlated flow through its design and verification platforms, Galaxy and Discovery. The focus on correlating the key building blocks and providing enhanced features to address design for manufacturing issues, has led to dramatic gains in overall productivity with improvements in design quality.
Aart de Geus
Chairman of the Board and Chief Executive Officer
Since co-founding Synopsys in 1986, Dr. Aart de Geus has expanded Synopsys from a start-up synthesis enterprise to a world leader in electronic design automation (EDA). As a technology visionary, he is frequently asked to speak on topics related to the electronics industry. As one of the leading experts on logic simulation and logic synthesis, Dr. de Geus was made a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in January 1999. He was also honored for pioneering the commercial logic synthesis market by being named the third recipient ever to receive the IEEE Circuits and Systems Society Industrial Pioneer Award. In 2002, shortly after transacting the largest merger in EDA history, Dr. de Geus was named CEO of the Year by Electronic Business magazine; and in 2004, Entrepreneur of the Year in IT for Northern California by Ernst & Young. Dr. de Geus is active in the business community as a member of the board of the Silicon Valley Leadership Group (SVLG), the Electronic Design Automation Consortium (EDAC), and the Fabless Semiconductor Association (FSA). He is also heavily involved in education for the next generation, having created in 1999 the Synopsys Outreach Foundation, which promotes project-based science and math learning throughout Silicon Valley.
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