Application-Specific ICs: Future Industry

In this second of two articles, Jerry Worchel, Senior Semiconductor Analyst with leading research firm In-Stat MDR, considers the future for ASIC design. Part 1 can be read here

While some may find this somewhat simplistic, the reality is, there are only two major first-level issues that will define the future evolution of our industry. First, technology will continue to evolve to allow for the innovation and deployment of next-generation devices, products and systems.

The second, which is rapidly becoming more important than the first, and will govern the extent to which technology will evolve, is economics. We have all seen the effects of economics in down years. Now and in the future, the costs associated with the development and deployment of future generations of technology will be limited more by economics than by technical capability. Even if we can develop the most advanced technology and products in the future, costs may make the product’s success uncertain at best.

Services and Media Key to Product Success
The semiconductor business today is facing challenges that really did not exist even 25 years ago. The success of products today often rests with the service sector, which supports the products’ operation and connectivity, and the peripheral suppliers that make the product viable. Two prime examples of this are the cellular handset and the DVD player. Without the wireless providers and DVD media manufacturers and distributors, neither of these products would have ever reached their current level of deployment and popularity. Even today, we still give away cellular handsets, with the profits of these sales going to the service providers, rather than to the handset manufacturers. And, this is the business model we all need to understand, for it will increasingly have an impact on how we do business.

Consumer Dominated Markets
Why are these factors so important? Because the consumer and not the business environment now controls the destiny of our industry, relative to the consumption of semiconductor products, and hence, the systems and products into which they are placed. This is another issue, in which dollar consumption numbers reported by World Semiconductor Trade Statistics (WSTS) can be very misleading. Per WSTS numbers, the consumer segment, as defined by the Semiconductor Industry Association (SIA), accounts for approximately 40% of all semiconductor consumption worldwide. Unfortunately, today that definition is severely flawed. There are many products that are not counted as consumer products, but should be. These include; cellular handsets, where the consumer accounts for between 85% and 90% of all purchases; desktop PCs, consumer accounts for 75+% of all purchases; even the laptop PC has surpassed the half way point relative to consumer purchases. The reality is that the consumer segment really controls about 70% of all semiconductor consumption.

With all these factors in mind, coupled with the rapidly increasing cost of next-generation technology, it becomes easy to recognize that the business and development models this industry has operated under, nearly since its inception, will have to change. While the industry’s technical prowess may remain unlimited, the economic limitations of the future may curtail many a technology from ever reaching its true potential.

Development Cost Grows as Design Rules Shrink
Total development cost has been increasing exponentially as design rules shrink. With the single exception of standard products, such as microprocessors and memory, the volume requirements for other products have dropped considerably from just ten years ago. In large part, this relates to both the rapid increase in product diversity and development costs, always coupled with time-to-market.

ASIC Figure 1
Figure 1. Non-Recurring Engineering By Design Rule Category (US$ in Millions) Source: In-Stat/MDR, 05/04

One of the major changes we have already seen, primarily to address cost and time-to-market issues, is the rise of the application-specific standard product. While this approach has gone a long way in at least addressing the cost issue, it is by no means the final solution. The increasing number of ASSP devices currently available translates directly to higher and more diverse inventory levels, which, as we are all aware, is also unacceptable.

The challenge now, as well as for the future, will be to develop a technology in which one design can meet many applications, thus amortizing its development costs over a larger application base. In addition, an approach such as this would enable the user to develop the next generation of customer-specific devices to meet next generation device requirements, as well as to define any number of ASSPs. A technology such as this would have definite advantages over any current day technology, including development boards.

While to some, this might imply that in the long-term development board usage would decline, fortunately, nothing could be further from the truth. The reality, in this case as it will be for most, is that for the majority of consumer-oriented products, the development board will remain the most cost effective and time-to-market effective approach for the foreseeable future.

The evolution to a better solution has already begun, via the availability of both structured ASIC and high-complexity FPGA technology. In fact it will be the merging of the two that will result in a product capable of designing both ASSP and customized solutions, while using the same basic silicon chip to meet multiple applications in both markets.

Table 1, below, presents a comparative analysis of the major logic-oriented, customer-specific design methodologies, for a variety of parameters. Comparison for all the stated parameters will be relative, for unless one compares all four methodologies for the exact same design, i.e., physical size, number of logic gates, type and size of memory, analog content, et cetera, no other comparison is possible. Using power as an example, a simple design will typically use far less power than a far more complex design.

Table 1. Customer-Specific Design Methodology Parametric Comparison

Gate Array Standard Cell User-Programmable Structured ASIC
Time-to-Market Fast Long Very Fast Fast
NRE Low High None-Low Low-Medium
Good-Very Good Excellent Good-Very Good Very Good-Excellent
Performance High Very High Medium-High High-Very High
Limited Yes No Yes
Power Moderate Moderate-High Moderate Moderate-High
Complexity Moderate-High High-Very High Simple-Very High Moderate-Very High
Cost Low-High Moderate-Very High Low-Moderate Low-Very High
Source: In-Stat/MDR, 05/04

And Finally – The Development Platform
The development platform, in the most basic of forms, is a standard product, which can be customized into another standard product or ASSP, or customized to meet the design requirements of a single customer.

ASIC Figure 2
Figure 2. ASIC/ASSP Market Evolution

The development platform will be used over a host of technologies and applications, initially in the top three end-use applications: electronic data processing, networking and wireless infrastructure.

While the density and complexity of these designs can run from the simple to the very complex, currently they tend to be on the very complex side. In this case, and for the most part, we are dealing with designs of one million gates and higher, mostly higher. However, and as we have seen in the past, all new technologies are very expensive to start, but as the technology is refined, and volumes grow, all sorts of opportunities will open up.

Since a development platform is nothing more than a development shrunk onto a single piece of silicon, it sounds very simple. It is not; for the definitions of what functions are included in that platform is key to the success of the platform. A wrong choice of incorporated functions, even in the definition of what functions to use to accomplish (re)programmability and (re)configurability, can quickly spell disaster. Currently, using the structured ASIC as an example, static RAM is most commonly used for programmability, and embedded blocks of gate array for configurability. While this is definitely a step forward from the classic ASIC, it will not meet the definition of the development platform, as it lacks configurability after device fabrication and packaging.

The next evolution of the structured ASIC will result in the first, primitive family of true development platforms, and that will be accomplished via the replacement of the gate array portion of the design, with an embedded FPGA, or possibly CPLD core(s). While static RAM will remain the memory of choice, we will see increasing use of embedded DRAM, but not via the use of conventional DRAM cores, instead via the use of the 1T-SRAM™, or as In-Stat/MDR refers to it, the pseudo DRAM. Beyond the pseudo DRAM, we will see an increasing use of embedded flash memory, as new architectures, with low write and erase voltages, which will not require either charge pumps or additional external power supplies, become available to the marketplace.

The customer-specific design, be it the structured ASIC of today, or the development platform of tomorrow, will come in a wide variety of flavors, and will not be in a “one flavor fits all” format. From a generic perspective, each of the major end-use markets; electronic data processing, communications, consumer, et cetera, will have their own requirements, with less than fifty percent commonality between any of the end-use markets. Even within any one of the major end-use markets, design content can vary greatly dependent upon which application(s) the development platform is targeted for. So, while designs destined for electronic data processing applications may contain an embedded MPU, as a centerpiece function, in the communications market, the centerpiece function is more apt to be the DSP.

So, what is really needed as the industry evolves to the development platform model, be it for the design of ASICs and/or ASSPs, is a new definition for the term design start. The bottom line relative to the use of the development platform is that, one design can meet 10, 20, 30 or more customer-specific and/or application-specific end-use applications.

So, is it one design start or multiple design starts?

Design Starts – Tomorrow’s Definition
Historically, and in specific regard to the customer-specific or ASIC design, the term design start referred to a single design, designed to one system-level application, for one customer. And, until a year ago that definition was valid.

Today, with the advent of structured ASIC technology, and its ultimate evolution into the “true” development platform, our methodology for counting design starts must be redefined. An excellent example of where a different approach to counting design starts has been employed for years is the high-end FPGA, where a standard device is customized by the end-user, possibly even more than once, with each being counted as a design start.

With the exception of the structured ASIC and user-programmable logic categories, all other semi-custom design approaches, from the standpoint of design starts, will all decline in the future. Design start numbers for user-programmable logic are usually estimates based solely on discussions with both suppliers and users. It is also important to recognize that design starts, like dollar shipments, follow SIA guidelines relative to ASIC designs, i.e., design starts include customer-specific designs using any one or more of the following approaches; cell-based, gate array, user-programmable logic and/or structured ASIC. But, in general, using current definitions, it is easy to understand why some analysts believe that the customer-specific or ASIC market is declining, at least with specific regard to design starts.

While one cannot argue with the data showing design starts declining, it all gets down to the definition. In-Stat/MDR firmly believes, when it comes to future customer-specific designs, that we must look at customer-specific design solutions (completions) rather than trying to count design starts. The same logic even applies to application-specific standard products, where one single platform can generate tens, if not hundreds, of ASSPs. The industry has finally come full circle, from the original breadboard of forty years ago, to the single-chip development platform of today, and more notably for tomorrow.

Figure 3, below, graphically compares design starts for customer-specific products that utilize the four design approaches previously stated (Table 1), plus those utilizing the development platform approach, over the 2002 thru 2010 time frame. You will see that the aggregate number of design starts went from a –0.7% CAGR between 2002 and 1010, not including the development platform, to a +1.4% over the same timeframe, including the development platform. And, that is using design starts in their classic form. If one were to take into account all the variations the end-user can define, be it as an ASIC or an ASSP, that growth rate, will in all probability more than quadruple that shown, over the forecast period, possibly even reaching ten times or more.

And they said ASIC designs were going away – no, they’re just changing, particularly with regard to the point of customization.

ASIC Figure 3
Figure 3. Future Customer-Specific Design Start Comparison by Design Methodology

One final point is that many people, even today, consider the FPGA to be a development platform, for in reality it is. However, these devices for the most part are software programmed, as opposed to the development platform described in this report, which, for the most part, is hard-core defined, thus optimizing performance, while at the same time reducing space, and possibly even cost.

Jerry Worchel
Senior Analyst - Semiconductor

Mr. Worchel, rejoined In-Stat/MDR in September 2001 as a senior analyst supporting the Semiconductor Industry, Emerging Semiconductor Applications and Digital Engines Services. Currently, Mr. Worchel has sole responsibility for the Digital Engines Service. Prior to rejoining In-Stat/MDR, Jerry was the Founder and President of inSearch Research, and brings with him over 35 years of semiconductor and related industry experience

Jerry has an MSEE from Brooklyn Polytechnic Institute, and holds several patents for various semiconductor process technologies he developed. He has been quoted in numerous publications, including The Wall Street Journal, San Jose Mercury News, Orange County Register, Computer Design Magazine, Electronic Engineering Times, Electronic News, Electronic Business News, Military and Aerospace Electronics, to name a few, as well as local papers. Jerry has also had articles published in Electronic Business Today, Electronic News, NASA Journal, and various IEEE Journals.

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©2007 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.

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By Jerry Worchel
 -In-Stat MDR
“The reality is that the consumer segment really controls about 70% of all semiconductor consumption.”

“And they said ASIC designs were going away – no, they’re just changing, particularly with regard to the point of customization.”