Software Development and SoC Verification
   on a Mixed-Level Model Platform

One major challenge in today's system-on-chip (SoC) designs is the ever-increasing amount of software, with more features and more interfaces to the underlying hardware. Abstract functional models are now an established technology that allows an early start to the software development process, and permits parallel development of software and hardware. However, the pure functional-modeling approach poses concerns in regards to timing accuracy, and consistency with the hardware models. This article discusses a way to address these concerns.

This article presents a solution that allows designers to use a mix of detailed, timed models with pure functional models to address timing-accuracy issues only where needed. By selectively extending the functional-modeling approach with interfaces that can be at the transaction level, or even the register-transfer level, this solution allows designers to minimize the impact on the overall simulation speed and ensure sufficient performance to execute the software development tasks.

With 90nm processes, new physical effects mean that the old ways of modeling delays are no longer accurate enough. For example, input capacitances have become more complex, interconnect net impedance dominates cell delay, and voltage drop across the device can have a significant affect on delays. Because both transistor drive capability and input capacitance are becoming more complex and non-linear at 90nm and below, a new approach to delay calculation is required.

However, to enable concurrent hardware and software development, it is necessary to ensure consistency between the functional models used for software development and the final hardware (RTL) models. This consistency can be achieved with today's verification technology. The solution presented here allows the development of testbenches with stimulus generators to drive the models and check for equivalent behavior, write assertions to check for incorrect or unanticipated behavior, and use functional-coverage tools to measure whether the tests exercise the design adequately.

With the mixed-abstraction-level modeling technology addressing the timing accuracy and performance issues, and the verification technology in place to address the consistency between abstract models and hardware models, a system is derived in which the hardware design can be verified with the actual software before tapeout.

Mixed-Level Modeling and Software Development
Abstract functional models offer distinct advantages for software development—simulation performance and early availability—both of which are a direct result of the modeling abstraction level. Simulation performance is crucial to run substantial amounts of software such as a modern operating system or a multimedia decoder. Early availability is important for starting the software development early enough in the project timeline, since the software development tasks often are on the critical path for product release.

Although today's model-development tools for pure functional models can enable the delivery of a full platform model within weeks, there are problems that cannot be solved with only an abstract functional model that has no—or incomplete—timing information.

The challenges include hardware or software tasks that depend on the timing, throughput, input rate, or other timing-related properties of a system. For these development tasks the entire model does not need to be timing accurate, but timing can be introduced only where it is needed, and thereby reduce the level of abstraction only for a fraction of the system.

The ability to compose a mix of functional and timed models, often referred to as hybrid or mixed-level modeling, and the capability to simulate such a model efficiently become more and more vital for today's SoC projects.

Tight integration of tools such as Synopsys' System Studio that support timing-accurate modeling with SystemC™ and Virtio Inc.'s functional-modeling technology allows such hybrid modeling, and enables a methodology that lets designers make the trade-offs between performance and accuracy.

This integration also addresses another key requirement for software development: the ability to interface and work with common software debuggers. Software developers have different debugger preferences, so a mixed-level verification platform has to provide interfaces to multiple software debuggers, and these interfaces have to operate together with the debuggers in the hardware and verification domains.

Mixed-Level Modeling and Verification
While it is a great benefit to have an accurate functional model or virtual prototype for software development available early in the design cycle, and many months before the hardware design has been completed, it also comes with a certain risk.

The functional model is built using the initial specification of the system. When architectures are being refined and the hardware (RTL) is being developed, changes may occur that affect that system specification. Therefore, the hardware and the functional model (used for software development) may get out of sync. This might be due to bug fixes, changes in the structure, or any of several other reasons.

If the consistency of the actual hardware that is being developed with the functional model cannot be ensured, there is a risk that the software will not function properly once the hardware design has been completed, defeating the purpose of concurrent hardware and software development. Hence, it is necessary to provide a verification environment that allows continuous integration of hardware and software. It is therefore mandatory to provide a common test and regression environment for the virtual prototype, mixed-level models, and the hardware platform to make sure these models are in sync.

A common test environment is possible if the testbenches are designed to participate in both cycle-accurate verification and abstract functional model verification. This can be achieved by a layered design in which the core of the testbench is functional and an adapter layer lets it participate in cycle-accurate model verification. Assertions can then verify consistent behavior of the cycle-accurate and functional models when exercised by the testbench.

Synopsys' Discovery™ Verification Platform is a prime example of such an integrated verification environment. It provides high-performance RTL simulation and the extensive testbench support required to build an infrastructure that can handle verification for the mixed-level modeling.

Mixed-Level Modeling in Practice
The Synopsys-Virtio partnership allows the use of System Studio, a SystemC-based architecture design and analysis environment, as an integrated development environment for mixed-level modeling. In System Studio it is possible to assemble and simulate models at different and mixed levels of abstraction, including Virtio's functional models, dataflow models, C/C++/SystemC models, and RTL models. Transaction-level models are attached to functional models with interfaces containing timing information to tailor the hardware architecture to the needs of its core applications (bandwidth, throughput, latency, buffer sizes, and so forth).

Synopsys and Virtio have implemented a mixed-level model for an LSI Logic CoreWare platform. This platform is based on an ARM926EJ-S core, which was modeled with an instruction accurate instruction-set simulator (ISS) from Virtio. All the peripherals were implemented with Virtio's functional modeling technology. Then a timed cycle-accurate model of the ARM AHB bus was inserted, written in SystemC, using Synopsys' System Studio. The architecture of this integration is depicted in Figure 1.

The SystemC AHB bus model is injected between the ISS and the peripherals (which are all functional models). The CPU is represented to the bus as a master component and all the functional peripheral models are represented to the bus as a slave component. The models are connected with transactors to the AHB bus. These transactors are responsible for converting transactions in one domain to the other. There are two types of transactors: Virtio to SystemC and SystemC to Virtio.

The cycle-accurate AHB bus model is given control of simulation when a transaction is pending and is updated with the simulation time before processing each transaction via a specially created interface. In order to minimize the impact of bus transactions on overall performance, the AHB bus model is connected only on the data bus, while the instruction bus remains in the high-level functional model.

A switch is implemented to further increase the performance. The switch allows disengaging the SystemC AHB bus model for high-performance tasks, for instance booting an operating system, and engaging the SystemC bus model again for performing specific tests after the OS is running. When switching from an abstract functional model to a timed model, a state transfer is needed between the two models. This may not always be a simple task as it may not be easy to infer the state of the abstract model from that of the timed one. Also, the state of the abstract model may map to more than one state of the timed model. To resolve this problem, the switch is only allowed to happen at times when the state of both models is known, such as when the bus is idle.

The current integration allows bus-analysis tasks to be performed during complex software operations such as booting Linux and running networking applications on top of it. Utilization of the AHB bus can be measured, for instance, by connecting System Studio monitors to the simulation.

The resulting system was able to boot Linux in 22 seconds when the SystemC AHB model was disengaged. The same task took 21 minutes with the AHB model engaged throughout, all on a 2.0-GHz x86 Linux host. The Linux image used executes 450 million instructions for the boot process, which translates to 20 MIPS for the functional model, and to 357 KIPS with the timed, cycle-accurate AHB model.

Even though the above performance numbers are preliminary and the integration still subject to further optimizations, the figures do point out the performance differences mentioned earlier, and do highlight the need for advanced mixed-level modeling technology, specifically to verify the hardware model in the presence of any substantial amount of software.

Mixed Level Figure 1
Figure 1: Mixed-level modeling example: using a cycle-accurate AHB model in a functional platform

Mixed-Level Enables Early Debug and Faster Design
This article has described how a mixed-level modeling technology addresses central issues in today's concurrent hardware and software development flows.

First, by using abstract functional models of the design, it is possible to develop and debug drivers, OS ports, and application software very early in the design cycle, many months before any hardware or prototype is available.

Second, the functional design can be refined by adding models with more detailed information, such as cycle-accurate timing and RTL implementations. Then the functional models and the software can be used as a testbench to provide realistic stimulus to the implementation models.

Third, testbench development can also start early in the design cycle, by attaching stimulus generators, assertions, and analysis tools to the functional models, and later applying the testbench to the actual RTL implementation models as they become available.

As a result, a mixed-level design and verification environment will speed up the design cycle, and reduce the number of bugs in hardware and software.

Markus Wloka is Director of Research & Development (R&D) for the Synopsys Verification Group in Herzogenrath, Germany. Wloka joined Synopsys in 1996, where he contributed to the COSSAP and System Studio system-level design tool. Prior to Synopsys, Wloka was employed by Motorola SPS in Tempe, Arizona in 1991, where he worked on the Entice standard cell characterization software, with a focus on distributed SPICE and power characterization. He received his Vordiplom in Informatik from Christian-Albrechts-Universitaet in Kiel, Germany in 1985, an M.S.C. in Computer Science in 1987 and a Ph.D. in Computer Science in 1991, both from Brown University, Providence, Rhode Island, USA.

Guy Shaviv, VP Engineering, Virtio Corp., has over 15 years of hands-on experience in software development and in successfully bringing software applications to market. His background includes positions for Interval Research, NASA Ames Research Center, SORBA Inc., and the IAF. Shaviv received his Ph.D. from the Technion - Israel Institute of Technology and has received a distinguished award from the National Research Council.

About Virtio
Virtio powers dramatic gains in software development by delivering early access to fast, full-function software emulation of embedded devices. Virtio is based in Campbell, California, in the USA with development centers in Campbell, the Alba Centre, Livingston, Scotland and Moscow, Russia.

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©2007 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.

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By Markus Wloka,
Synopsys GmbH
Guy Shaviv,
Virtio Corp

 -Virtio-Synopsys Collaboration

"Mixed-level modeling ensures sufficient performance to execute software development tasks."