The Three Ps:
Key Characteristics for Success
What is it that drives the semiconductor industry to success? Aart de Geus, CEO and Chairman, Synopsys, explores recent trends in process geometry development, and the growing number of technical challenges that designers face today.
Designers have become adept at meeting evolving requirements as they transition from one chip development project to the next. While new challenges emerge, some of the success factors have remained constant for some time. The ‘three Ps’ framework encapsulates the key issues.
The first of these is performance. In the widest sense, performance typically focuses on three optimization functions: speed, area and power. Over the last 40 years, the raw performance of many chip designs has remained a key characteristic for success. The second P is productivity, by which is meant the cost and engineering effort built into reaching a certain objective. The importance of productivity has grown dramatically in the last few years.
These first two Ps always trade off against one another: you can easily increase productivity by reducing the device speed, for instance. Our third characteristic, then, is predictability – the statistical variation on the other two Ps. In other words, bringing a product to market on time and within budget.
The focus on each of the three Ps varies according to who you are speaking to within a company. Typically, the engineers concentrate on performance: they want to know if they can get the speed that they need (or meet the power budget). Middle management is usually concerned about productivity: they want to know how much budget they have, how much effort it will take, and when they can get the speed that they need. The top level of management focuses on predictability: they want to know if they will ever get to the speed that they need. They want to ensure that they fulfill their commitment to their customers and that the chip is rolled out successfully and on a timely basis.
Facing Technical Challenges
The three Ps model provides three axes upon which solutions can be developed. Needless to say, there are many technical challenges to overcome. The first of these is verification, which is often cited as taking 60-65 percent of the overall design time. Here, the challenge is that the problem is growing far more rapidly than Moore’s Law. The obvious quick fix is to use significant pre-verified IP that works really well, but if the IP doesn’t work you have an even bigger problem.
Figure 1: The Three Ps of Predictable Success
A second big challenge is timing and optimization – we have been living with this problem for a while, and have some effective strategies in place. Signal integrity is also an important concern – while it pushes the traditional digital paradigm more and more towards an analog problem, our job is to push it back – because it’s really in digital design that we’ve seen the biggest improvement in productivity in the last 40 years.
Then there are power-related challenges to overcome. In one sense, timing and power have become equivalent optimization factors: most people would say that, at this point in time, the increases in speed are primarily limited by the ability to dissipate the power or to get the power where it’s needed. By power, we refer to both dynamic power and leakage power. Of course, dynamic power grows with the number of transistors and with the frequency. Although we’ve brought the voltage down in the last ten years, we’re trying to bring it down much further. Leakage power is now a very important ingredient at the smaller geometries of 90nm and 65nm.
In the design for manufacture (DFM) arena, there are problems concerning printability, mask-making and the actual yields achieved when you are in manufacture. Here, the challenge is that the feature size is now significantly shorter than the wavelength of light. The wavelength of light is 193nm and yet we’re talking about routinely manufacturing 65nm transistors and below.
Synopsys Strategy for Predictable Success
The technical challenges described above have driven a number of changes in Synopsys’ products. Fundamentally, our current strategy reflects the fact that these problems are now completely interdependent, and each must be dealt with as part of the bigger picture.
Synopsys started in synthesis, but we moved towards a complete flow that incorporated the two mainstays of traditional EDA: design and verification. A few years ago, it became increasingly clear that, as geometries became smaller, we would begin to see the dominance of sub-micron physical effects to the design flow. Gone are the days when you could say, “Here are the netlists. Just ship it to the fab.”
If there’s one very strong link that’s necessary, it is the link between implementation and DFM. As we transition to smaller geometries, and it becomes possible to put more and more functionality on a chip, some shortcuts are needed in order to design all of this functionality within a reasonable timeframe. IP reuse is an obvious shortcut that is very much in use today. One of the key requirements is to make sure that the IP is of the highest quality.
The clear need to have more optimized flows is the essence of the Synopsys strategy of the last six or seven years. We recognize the importance of having a complete solution where all the pieces correlate together and are capable of optimizing simultaneously and concurrently to meet the design targets. Synopsys tools address this requirement: Galaxy for implementation, Discovery for verification, a comprehensive set of IP solutions, and a set of tools for DFM.
The Move to Smaller Geometries
The implementation trends in Figure 2 below show that, over the course of the last four years, the percentage of chips that are designed at smaller geometries has increased, while the use of larger geometries is in decline. This transition is a gradual one: the center of gravity is currently 180nm and 90nm, and statistics from foundry partners such as TSMC and UMC show that the bulk of designs will move to 90nm during 2006. However, it is interesting to note that, for the designers that we deal with most, the move to 90nm is actually quite rapid, and there is also significant progress towards 65nm.
Figure 2: Transition to Smaller Geometries
As this trend progresses, we are faced with more and more design challenges. For the last 20 years, the key technical issues have primarily revolved around timing and area. Around the era of 250nm designs, we started to see that optimization for power was becoming an issue as a result of increased demand for wireless products – especially cellular phones.
Figure 3: Design Challenges Are Still Increasing
Something fundamental happens at 180nm: there is great focus on timing closure. This is because, between 250nm and 180nm, the dominant delay is due to the distance from the gates to the interconnect. At these geometries, it is necessary to perform synthesis in order to understand the actual placement.
As we moved to 130nm, signal integrity suddenly became a major issue. The move to 130nm, with the introduction of copper and low-K dielectrics was somewhat traumatic for the entire manufacturing industry. At the 130nm node we encountered additional delays of over a year, compared to our expected transition time to the next process node. Today, however, 130nm is yielding well, and many people are designing at those geometries.
As a matter of fact, many have moved as far as 90nm. Largely because 130nm was such a bad surprise, 90nm has been a good surprise, and has brought with it much emphasis on bringing the yield up rapidly and achieving predictable results. There is, however, a new challenge at 90nm: leakage. Because of this, it is important to be able to incorporate a deep understanding of power in all of the optimizations down the chain.
As we gradually move forward towards 65nm and the first 45nm designs, we are entering a much more statistical world. Understanding variability will become important in achieving predictable designs. We have seen that all of the 65nm designs that we’ve dealt with so far have done reasonably well without needing a fine degree of variation calculation. For 45nm, I would expect that we will see the necessity to deal with that in a much more detailed fashion.
The Need to Optimize Design Flow
To drive the industry to success at smaller geometries, we have to address how best to optimize the design flow, how to boost verification, and how to increase predictability. With a complete and correlated flow that recognizes the fact that design issues are interdependent, it will be easier to achieve these goals on the path to 65nm and beyond.
About Aart de Geus
Chairman of the Board and Chief Executive Officer
Since co-founding Synopsys in 1986, Dr. Aart de Geus has expanded Synopsys from a start-up synthesis enterprise to a world leader in electronic design automation (EDA). As a technology visionary, he is frequently asked to speak on topics related to the electronics industry. As one of the leading experts on logic simulation and logic synthesis, Dr. de Geus was made a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in January 1999. He was also honored for pioneering the commercial logic synthesis market by being named the third recipient ever to receive the IEEE Circuits and Systems Society Industrial Pioneer Award. In 2002, shortly after transacting the largest merger in EDA history, Dr. de Geus was named CEO of the Year by Electronic Business magazine; and in 2004, Entrepreneur of the Year in IT for Northern California by Ernst & Young. Dr. de Geus is active in the business community as a member of the board of the Silicon Valley Leadership Group (SVLG), the Electronic Design Automation Consortium (EDAC), and the Fabless Semiconductor Association (FSA). He is also heavily involved in education for the next generation, having created in 1999 the Synopsys Outreach Foundation, which promotes project-based science and math learning throughout Silicon Valley.
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