Integrating DFM in the Design Flow
Recent collaboration between UMC and Synopsys has resulted in a complete RTL-to-GDSII reference design flow, which now includes critical design for manufacturing features for UMC’s 90nm process. Suzanna Chang, Senior Director of Marketing for UMC, and Paul Lai, Group Manager of Strategic Alliances, Synopsys, explain how the use of this flow can help designers reduce design risk and speed time to results.

UMC's Design for Manufacturing (DFM) efforts supplement the basic design work that is performed to support customers. This helps increase the chances of first time silicon success, which is critical in reducing time to market and overall costs at technologies of 90nm and below. Improved DFM solutions help customers realize enhanced yields, faster turnaround times, and reduced risk and uncertainty to ultimately lower development costs.

Synopsys Professional Services and UMC have worked closely together to develop the complete RTL-to-GDSII design flow, which is based on Synopsys Galaxy™ Design Platform. This collaboration builds upon UMC’s advanced technology and Synopsys’ proven expertise in design flows and provides customers with access to an optimized flow that delivers high quality, low-power system-on-chip (SoC) designs, while speeding time to results.

The latest release of the Galaxy Design Platform includes many new capabilities, including advanced floor planning, multiple threshold voltage leakage power optimization, signal integrity analysis, and tighter design for manufacturing (DFM) links, all of which can be used with UMC’s 90nm process. The reference design flow has been validated using ARM’s Artisan® SAGE-X™ production-proven UMC 90nm standard cell library. This allows UMC customers to have access to a validated reference flow tailored to UMC’s advanced 90nm process.

Advanced Floorplanning Capabilities
The reference flow includes the advanced capabilities of Synopsys’ JupiterXT™ design planning solution, and Synopsys’ Power Network Synthesis (PNS) and Power Network Analysis (PNA) products, which are used to design the power plan at the floorplanning stage. Other capabilities include virtual-flat floorplanning with physical hierarchy-aware global routing, virtual timing optimization, and macro placement with automatic hierarchy detection. Designers can create an optimized initial design floor plan using these advanced features to guide them to the next design steps in physical synthesis and place and route. This approach helps to avoid design iterations and timing closure issues.

Figure 1
Figure 1: UMC-Synopsys 90nm Reference Design Flow

The reference design flow also features multiple threshold (MVth) voltage leakage power optimization to take advantage of the UMC 90nm multiple threshold libraries that are available. In addition, the flow supports advanced signal integrity capabilities to perform analysis for electro migration (EM) and voltage drop (IR). Both of these issues are critical causes of failure at designs of 90nm and below.

DFM Integration
Synopsys has worked with UMC to add several new capabilities that are supported and validated in the 90nm UMC reference design flow. These support metal insertion and meet UMC’s metal density requirements, and perform automatic redundant VIA insertions and VIA farm insertions. All of these DFM capabilities result in improved reliability based on UMC’s 90nm design guidelines, and are supported in Synopsys’ Astro™ place and route tool.

Figure 2
Before dummy metal filling
Figure 2
After dummy metal filling
Figure 2
Before swapping via(s)
Figure 2
Redundant vias inserted

Synopsys’ Astro has been enhanced to work with 90nm and 65nm technologies. Support for advanced process technology is provided by adding enhancements to the Astro router and technology file. DFM issues are easier to manage at the routing stage, with support for proper technology file definition.

Consistency and Repeatability Across the Flow
The central benefit of deploying a reference flow is the ability to build a design in the shortest time by automating as many of the project tasks as possible. By minimizing the amount of manual intervention required, a primary source of errors can be eliminated. Deploying a reference flow will provide consistent reports and logfiles for all designs, ensuring that audit support is provided. In addition, consistent structure for all data across designs and design sub-blocks, which comes from having a standardized environment, means that implementation is more easily shared between different design teams. All of these factors help to ensure design repeatability and consistency across the flow.

The reference flow provides end-users with a powerful “jump-start” on a complete RTL2GDSII design process. Example tool scripts are provided for all tasks in the flow, which also enables non-experts to be able to run all of the tools. The use of ‘pass/fail’ files allows control of the design process to be automated based on requirements and exceptions that are present in tool log files. For example, the presence of error messages can be detected and used as checks in controlling the process. Other more advanced and customizable checks are possible.

Synopsys’ expertise in design methodology and UMC’s advanced process technology are brought together for the benefit of the design community within the reference design flow. As well as delivering advanced features such as automated chip synthesis, sophisticated power optimization and signal integrity sign-off, this new flow encapsulates UMC’s advanced DFM design rules at the floorplanning stage. This integration of DFM capabilities early in the design flow results in improved reliability for designs implemented in UMC’s 90nm process, which ultimately means high quality ICs while speeding time to results.

Flow Highlights
  • Built on Synopsys Galaxy™ Design and Discovery™ Verification Platforms by Synopsys Professional Services, based on a production-proven design methodology.
  • Flow has been proven using the LEON2 32-bit RISC CPU, developed by Gaisler Research, as a reference design. The core consists of a SPARC-V8 compliant 32-bit RISC CPU, industrial-standard AMBA system buses, 10/100 Ethernet MAC, and industrial-standard PCI interfaces. This high-performance and highly configurable core allows the addition of further digital and analog-mixed signal AMS hard IP.
  • Enables designers to resolve VDSM design bottlenecks associated with power network synthesis, power network analysis, IR drop and electro-migration (EM) analysis, signal integrity (SI) and crosstalk analysis.

  • Supports critical UMC 90nm design for manufacturing (DFM) design rules and design guidelines using Synopsys Astro physical implementation tool.
  • Supports multiple hierarchical design approach to address chip complexity and enable efficient management and sharing of a large amount of design data.

The UMC/Synopsys reference design flow is available now and can be accessed from UMC's website at

About UMC
UMC (NYSE: UMC, TSE: 2303) is a leading global semiconductor foundry that manufactures advanced process ICs for applications spanning every major sector of the semiconductor industry. UMC delivers cutting-edge foundry technologies that enable sophisticated system-on-chip (SoC) designs, including volume production 90nm, industry-leading 65nm, and mixed signal/RFCMOS. UMC’s 10 wafer manufacturing facilities include two advanced 300mm fabs; Fab 12A in Taiwan and Singapore-based Fab 12i are both in volume production for a variety of customer products. The company employs approximately 10,500 people worldwide and has offices in Taiwan, Japan, Singapore, Europe, and the United States. UMC can be found on the web at

About Suzanna Chang, Senior Director of Marketing UMC
Suzanna joined UMC in 2000. She has over 16 years experience in the Semiconductor and EDA industries She has extensive knowledge in the ASIC/COT arenas. Prior to UMC, she worked at LSI Logic, Aspec Technology and Synopsys. She hold a BS in Electrical and Computer Engineering and BA in Spanish from UC Davis.

About Paul Lai, Group Manager Strategic Alliances, Synopsys
Paul is a veteran in the EDA industry with over 15 years experience. Prior to Synopsys he held various management positions in applications, marketing, and strategic programs at Gateway Design Automation, Cadence, and Viewlogic. Currently, he manages the Synopsys strategic alliance program with key foundries, such as TSMC. Paul earned B.S.E.E. and M.S.E.E degrees from Texas A&M University and an MBA degree from the University of California, Berkeley.

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©2007 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.

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