Success Stories 

富士通研究所、シノプシスのProcessor Designer を用いて3G/LTEモデム向けカスタム・プロセッサを開発
今回、当社のカスタムDSP の設計にProcessor Designer を導入する大きな決め手となったのは、カスタム・プロセッサ設計ツールのプロバイダとしてのシノプシスの実績でした。この強力なツールによってソフトウェア・ツール・チェーン開発の負担が 軽減したため、チップの設計目標を達成する作業に専念できました。”
毛利 真寿 氏, 主任研究員、ユビキタスプラットフォーム研究所 エンベデッドプラットフォーム研究部, 株式会社富士通研究所

リコー、シノプシスのPlatform Architect MCOを用いて新しい多機能プリンタ(MFP)向けSoCアーキテクチャを最適化
当社では、Platform Architect MCO とVirtualizer を用いることで、仮想プラットフォームの迅速な構築、アーキテクチャの検討とソフトウェアの早期開発、さらに最上位のSoC 全体としてのハードウェア性能検証が可能になりました。
青木 賢 氏, EPF開発室, 株式会社リコー

Ricoh Delivers Software 5 Months in Advance for New Multi-Function Printer with Synopsys Virtualizer
Using Platform Architect™ MCO & Virtualizer™, we can build a virtual platform sooner, enabling architecture exploration, early software development and hardware performance verification at the highest level of the design phase for our SoC design.
Satoshi Aoki, Embedded Platform Development Department, Ricoh Company, Ltd.

Altera's SoC FPGA Virtual Target Enables Early Software Development and High Debug Productivity
Being able to deliver a Virtual Target based on Synopsys' virtual prototyping technology is key to helping our customers address the growing software complexity in their SoC FPGA-based designs.
Vince Hu, Vice President of Product and Corporate Marketing, Altera Corporation

Peking University - NELVT Utilizes Complete Hardware + Software HAPS FPGA-Based Prototyping Solution for HDTV 1080P Encoder Design
We trust the HAPS system to provide reliably high performance. Because Synopsys' solution includes an integrated hardware plus software flow and great technical support, we save time and money
Dr. Huizhu Jia, SoC team leader of the National Engineering Laboratory for Video Technology (NELVT), Peking University

富士通、LTE対応最新RF トランシーバの早期製品化のためにSPWを採用
複数規格に準拠したトランシーバには高い柔軟性が求められており、複雑化も進んでいますが、シノプシスのSPWは常に、予算の範囲内でスケジュールどおりのテープアウトを可能にしてくれます。
Vivek Bhan 氏, 上級副社長, Fujitsu Semiconductor Wireless Products, Inc.

ヤマハ、Processor Designerの活用によりXMP-1 DSPの搭載機能を従来比2倍に増やし、かつテープアウトまでの期間を6カ月短縮
“Processor Designerの活用により、この高精度サウンド・ジェネレーションDSPに従来比 2倍の機能を搭載し、開発コストは削減しつつ、必要となるソフトウェア開発ツール群の生成まで含めてちょうど1年ですべての開発を終了しました。“
森島 守人 氏, 半導体事業部商品開発部 デバイス開発第1グループ 技師, ヤマハ株式会社

STMicroelectronics – Rapid Delivery of Demodulator IP for Analog TV Standards using Synphony Model Compiler
By using Synopsys' Synphony Model Compiler we were able to complete our entire validation effort within two weeks and with extremely reliable results.
Srevats Laxman, Technical Leader IP Algorithms, STMicroelectronics

Space Systems/Loral Selects Trusted SPW Tool for Advanced Satellite Receiver Design
SPW's fast simulation runtime is critical to keeping up project momentum and reducing overall development time. The ability to design an optimal signal processing algorithm in the shortest amount of time with less effort is the most significant benefit SPW offers.
Charan Langton, Manager of Simulation and Analysis, Space Systems / Loral

Processor Designerの設計自動化フローを活用しOA機器向けカスタムDSPの開発期間短縮に成功したリコー
“Processor Designerを利用することで、RTLやソフトウェア開発ツール群の生成といった詳細な作業に煩わされることなくデザインに専念でき、高品質なカスタムDSPを簡単に開発できます。これは、まさに私たちが求めていたものでした“
木村貞弘 氏, 研究開発本部 基盤技術研究センター 主幹研究員, 株式会社リコー

NXP - Multicore Optimization Technology in Platform Architect Enables NXP to Analyze System-level Performance and Reduce Cycle Time
Platform Architect allows us to define the optimum system architecture supporting all desired application use-cases in a cost-effective way.
Rene van den Berg, System Architect, Car Entertainment Solutions, NXP Semiconductors

CEVAのMM3000モバイル・マルチメディア・プラットフォームの開発でProcessor Designerを活用し2つの先進的なDSP設計を実現
“MM3000のような革新的なデザインにとって最適な実装に欠かせないツール・フロー統合や柔軟性を提供できる“ ツールはProcessor Designerしかありませんでした
Erez Bar-Niv, CTO, CEVA

JAXA – SPW Enables 3-4X Faster Algorithm Design Flow for Modem Design
Designing an optimal system in the shortest amount of time, with minimal effort and cost, is the biggest benefit that SPW provides. It would probably take 3-4 times the effort without SPW.
Naohiko Iwakiri, Senior Research Scientist of Tokyo University, and Institute of Space and Astronautical Science, JAXA

InterDigital Designs Standards-Compliant, Flexible HSPA Solution Using SPW Tools and Models
For InterDigital the design process determines our success. We needed a modeling methodology covering the needs of the entire interdisciplinary team. We relied on Synopsys' algorithm design solution to put this rigorous process in place.
Robert Peloso, Director, Engineering Management, InterDigital

Stellamar – All-Digital ADC a Design Success with SPW Algorithm Design Tool
Synopsys is a key partner in helping us innovate. Synopsys SPW gives us the ability and confidence to focus on what differentiates our product and gets us to market faster.
Allan Chin, CEO, Stellamar

Teradici – ASIC Prototyping Made Fast and Efficient with Synplify Premier
Other tools can't handle the complex constructs of the ASICs we're working on. Only Synplify Premier gives us the ability to synthesize native ASIC code untouched for our FPGA prototype.
David Garau, Engineering Manager, Silicon Validation Group, Teradici

Phonak: Synopsys Professional Services Helps Phonak Establish Rapid Prototyping Flow for Ultra Low Power Designs
The cooperation with Synopsys Professional Services helped us to successfully complete our FPGA emulation project for the next-generation platform of hearing aid devices and get an early start on software development. The collaboration was marked by very efficient communication, timely responses and quick adaptation to changes in project objectives.
Vesselin Parushev, Project Leader, Microsystems, Phonak AG

Maxtek: Maxtek Leverages Synopsys’ Services and ASIC Prototyping Solutions to Develop 12.5 GS/s Digital Receiver
Using Synopsys Professional Services was the best choice for achieving our project’s high-performance objectives. Their FPGA design experience and prototyping expertise were key factors in our decision, and more importantly, in achieving our aggressive project objectives.
Gary Goncher, System Architect, Data Converters, Maxtek Components Corporation

STMicroelectronics Noida Quickly Achieves Advanced Video Compression with Synphony C Compiler
Even with no RTL experience, we were able to complete this complex digital video hardware IP design in 9 months with two engineers.
Ravin Sachdeva, Technical Leader, STMicroelectronics

STMicroelectronics – High-Level Synthesis Flow Achieves Higher Reliability and Productivity for Multirate Digital IF TV ASIC
Synphony Model Compiler really improved our productivity and reliability in designing complex multi-rate DSP algorithm, mixed-signal functions and generated very reliable results.
François Rémond, CAD & Design Methodology Director, Home Entertainment & Displays Group, STMicroelectronics

横河電機、Processor Designerで業界最高速のプログラマブル・ロジック・コントローラ(PLC)を実現
“横河電機の PLC、FA-M3Vは業界最高速の動作を実現しましたProcessor Designerでこれほど高性能な特定用途向け組込みプロセッサが開発できることは、システム設計エンジニアの間でも“
岡本 弘文 氏, PLC技術部 4グループ長, 横河電機株式会社

Texas Instruments – Synopsys Delivers Software Developer Productivity Gains and Reduced Development Cycles
Synopsys & Texas Instruments Synopsys Delivers Software Developer Productivity Gains and Reduced Development Cycles
Synopsys & Texas Instruments, TI Worldwide Director of Marketing, Cellular Systems



NewsArticlesBlogsDatasheetsSuccess StoriesWhite PapersWebinarsNewsletters