White Papers 



PCI Express IPを活用した3つの省電力手法
本稿ではPCI Express IPで利用できる3つの省電力手法をご紹介し、プロトコル自体および設計ツールのパワー・マネージメント機能を使用することによって、復帰時間の要件を満たしつつSoCの消費電力を削減する方法についてご説明します。
Athul Sripad, ASIC Digital Design Engineer, Synopsys

高速でスケーラブルなセンサー接続を実現する MIPI I3C
MIPI® Allianceは現在、I2CとSPIそれぞれの長所を兼ね備えたI3C(SenseWire)と呼ばれる新しい標準規格の策定を進めています。MIPI I3CはI2CとSPIの機能と性能を高めつつ、ピン数を抑えた包括的かつスケーラブルなインターフェイスおよびアーキテクチャです。I3Cは、モバイル機器やその影響を受けたアプリケーション、さらには組込みシステム・アプリケーションで近い将来必須となることが予想されるセンサー・インターフェイス・アーキテクチャをサポートします。本稿ではMIPI I3C仕様の概要、およびI2CからI3Cへのシームレスな移行を可能に する利点についてご説明します。
Sriram Balasubramanian, Sr. Manager, IP R&D, Synopsys; Hezi Saar, Staff Product Marketing Manager, Synopsys

Securing the Internet of Things
Security is a key requirement for Internet of Things (IoT) devices and must be considered for all aspects of the design. This paper provides an overview of security basics, feature requirements, technical solutions, and associated system-level trade-offs for implementing security in IoT devices. Making the required trade-offs is significantly easier by leveraging secure, proven building blocks that were designed with secure systems in mind and optimized for low footprint and energy. This paper can help you decide on the optimal mix of features and best tradeoffs to make for your specific IoT device that will result in a secure architecture that can be efficiently implemented.
Ruud Derwig, Senior Staff Engineer, Synopsys

Foundation IP for 7nm FinFETs: Design and Implementation
Learn about the challenges of IP design and implementation for 7nm FinFETs. Along with the performance and area benefits that the node brings, designers must understand the significant technical challenges stemming from increasing variability associated with tighter pitches and more complex lithography steps. Design for variability and reliability considerations will require comprehensive modeling and analysis as well as advanced circuit techniques such as on chip sensing and compensation.
Jamil Kawa, Synopsys Fellow, Synopsys

LPDDR4の性能と消費電力を最適化する マルチチャネル・アーキテクチャ
LPDDR4は小型・薄型パッケージで圧倒的な帯域幅を実現しており、データ・レート3,200Mbpsの場合、2ダイ1パッケージの15x15mm LPDDR4 1個で最大25.6GB/sの帯域幅が得られます。LPDDR4は新しい機能の追加とアーキテクチャの大幅な刷新により、LPDDR2およびLPDDR3からさらなる発展を遂げています。
Marc Greenberg, Director of Product Marketing for DDR IP, Synopsys

USB Type-Cの実装に関する3つの課題とその対処
USB Type-CをSoCに組み込むにあたって設計者が直面するのは、デザイン分割の問題です。ハードウェア設計に当たっては、アナログ回路および高電圧/大電流スイッチに関する要求事項を満たせるように、SoCとシステム・デザインを分割する必要があります。また、メイン・プロセッサ、内部マイクロコントローラ、電源管理IC内のマイクロコントローラ、外部の専用USBType-Cチップのいずれかで実行できるように、USB Type-C管理ソフトウェアを分割する必要もあります。本稿では、USB Type-Cを組み込んだSoC設計者の皆様に、これらの設計課題の詳細と解決方法をご説明します。
Morten Christiansen, Technical Marketing Manager, USB, Synopsys

Designing an Efficient DSP Solution: Choosing the Right Processor and Software Development Toolchain
Read about key challenges in DSP implementation from both hardware and software application perspectives, and learn how a properly selected and configured DSP processor coupled with an advanced software development toolchain can overcome these challenges. This white paper describes how to generate tight, efficient, and maintainable DSP code for a platform consisting of an IP core based on a specialized instruction-set architecture (ISA) coupled with a DSP-aware toolchain.
Abhishek Bit, CAE, Synopsys; Jamie Campbell, CAE, Synopsys; Sergey Yakushkin, R&D Engineer, Synopsys

Delivering High Quality Analog Video Signals with Optimized Video DACs
In most modern consumer equipment, multimedia content is processed in the digital domain. However, analog video transmission requires the digital video content conversion to the analog domain. To accomplish this, a video digital-to-analog (DAC) must be used. This paper outlines the most common analog video signal standard-specifications that multimedia SoCs must support. It describes the key characteristics and features of a DAC solution optimized for video applications. The paper addresses system-level techniques that together with an optimized video DAC will enable SoC designers to deliver power-efficient and feature-rich multimedia devices.
Antonio Leal, Analog Design Manager, Synopsys

完全にセキュアなシステムを実現する真性乱数生成器(TRNG)
ほとんどのコンピュータやデジタル家電、そしてIoT(Internet of Thing) と称されるさまざまな機器など、暗号を利用したセキュリティ機構を必要とする機器は身の回りにすさまじく増加しています。事実、PlayStationやXboxといったゲーム機や玩具にさえ、驚くほど複雑なセキュリティ機能が内蔵されています。
David A. Jones, Senior FAE, Synopsys

Safety in SoCs: Accelerating the Road to ISO 26262 Certification With Processor IP
Today’s system-on-chip (SoC) designs are becoming more complex, increasing the pressure on verification and design teams to deliver fully functional designs. Recent studies have shown that over 50% of the development time on a complex IC is now being spent on verification, revealing the severity of the problem project teams are facing. As more SoC designs are used in electronic systems deployed in safety-critical applications, adhering to functional safety standards such as ISO 26262 has become an important consideration when defining the verification methodology. This white paper outlines the key requirements for ISO 26262 certification and demonstrates how to accelerate the development of safety-critical IP and SoCs through the use of out-of-the-box safety-ready IP with advanced verification qualification tools and methodologies.
Steven Parkinson, R&D Engineer, Synopsys

Design, Test & Repair Methodology for FinFET-Based Memories
The advent of FinFET-based memories presents new memory test challenges. This white paper covers the new design complexities, defect coverage and yield challenges presented by FinFET-based memories; how to synthesize test algorithms for detection and diagnosis of FinFET specific memory defects; and how incorporating built-in self-test (BIST) infrastructures with high-efficiency test and repair capabilities can help to ensure high yield for FinFET-based memories.
Dr. Yervant Zorian, Chief Architect and Fellow, Synopsys

Anatomy of the HDMI IP Certification Flow
HDMI IP plays a critical role in enabling HDMI 2.0 features, making 60 frames per second UHD video and audio possible in multimedia SoCs. SoC designers can avoid costly functionality and interoperability issues by selecting and integrating HDMI IP that has gone through an extensive multi-phase testing process and achieved certification. This white paper outlines the HDMI IP certification flow from internal quality, functionality and interoperability testing to certification of the latest HDMI Compliance Test Specification (CTS) at an Authorized Test Center (ATC).
Dr. Antonio J. Salazar E., ASIC Digital Design Engineer, Synopsys; Hugo Faria, Embedded Software and Protocol Validation Engineer, Synopsys; Quintin D. Anderson, Co-Founder and COO, Granite River Labs

Using an Embedded Vision Processor to Build an Efficient Object Recognition System
The advent of high-performance mobile computing platforms is driving rapid progress in computer vision capabilities. Machine vision is becoming embedded in highly integrated SoCs and expanding into emerging high-volume consumer applications such as home surveillance, games, and automotive safety. A major challenge in enabling mass adoption of embedded vision applications is providing the processing capability at a power and cost point low enough for mobile consumer applications, while maintaining sufficient flexibility to cater to rapidly evolving markets. Read this whitepaper to understand the challenges of efficiently implementing an embedded vision system, explore an object detection application example and learn about the DesignWare Embedded Vision Processor Family.
James Campbell, CAE, Synopsys; Valeriy Kazantsev, CAE, Synopsys

Virtualizing Cloud Computing With Optimized IP for NFV SoCs
The growth in internet traffic is impacting how cloud and carrier data center operators design their compute and data networking architectures. To meet the application demands for scale-out servers and networks, designers are implementing virtual environments such as Network Function Virtualization (NFV) to achieve higher efficiency and lower the cost and time of deploying the new applications. This paper discusses how using the right IP accelerates the implementation of SoCs used in NFV systems.
Ron DiGiuseppe, Senior Strategic Marketing Manager, Synopsys

PCI Express 4.0 Controller Design and Integration Challenges
Designers need to start planning for PCI Express 4.0 integration now, because decisions for the PCIe 4.0 controller can have far-reaching consequences for the entire SoC. This paper describes the market adoption and expected use of PCIe 4.0; covers the specification; and discusses three challenges the new specification brings to controller designers.
Scott Knowlton, Sr. Product Marketing Manager, DesignWare Controller IP for PCI Express; Richard Solomon, Sr. Technical Marketing Manager, DesignWare Controller IP for PCI Express

Rapid Architectural Exploration in Designing Application-Specific Processors
Today’s SoCs demand increasing performance with high energy efficiency, but yet require flexibility to address late specification changes, post-silicon modifications and product derivatives. ASIPs close the gap between highly optimized fixed-hardware data path implementations and standard processor IP, and efficient architectural exploration is at the heart of any ASIP design process. Designers need to rapidly explore the impact of different architectural choices on power consumption and performance, ideally using real-world application C-code as part of the design flow. This white paper explains the architectural tradeoffs that are available to an ASIP designer, how to trade off performance vs. area, and why an ASIP design can still maintain full C-programmability while being optimized for a certain application domain. We will illustrate the architectural exploration approach using a simple yet representative example.
Bo Wu, Technical Marketing Manager, Synopsys; Markus Willems, Product Marketing Manager, Synopsys

Ethernetとコネクテッド・ワールド
本稿では、住宅、自動車、データセンターという3つの主要な市場におけるネットワーキングの最新動向を概観し、 それぞれの市場でEthernet が果たす役割についてご説明します。また、Ethernetベースのデジタル・コントローラおよび PHYを短期間で確実にシステム・オン・チップ(SoC)に実装していただけるよう、ユーザー・ニーズに応えてシノプシスが 開発したコンフィギュラブルな半導体IPもご紹介します。
John A. Swanson, Ethernet Product Line Manager, Synopsys

IP統合とソフトウェア開発への取り組みによるSoC開発期間の短縮
本稿では、SoC 設計者がSoC の複雑性や開発期間の課題に取り組む上で直面する問題について掘り下げて いきます。サードパーティー製IP の使用について論じる一方、今日ではSoC の複雑性により、単に高品質な IP を用意しただけでは開発期間の短縮は望めなくなっている点についても言及します。また、IP のドライバ・ ソフトウェアの開発に関連する問題も取り上げます。最後に、あらゆるSoC 設計に対応する5 つの主要な開発 ステップについて概観し、サードパーティーのIP ベンダによるそれぞれのステップの短縮の見込みについて 述べたいと思います。
Dr. Johannes Stahl, Director of Prototyping Product Marketing, Synopsys, Inc.

Real-Time Trace: A Better Way to Debug Embedded Applications
Firmware and application software development is often the critical path for many embedded designs. Problems that appear in the late phases of the development can be extremely difficult to track down and debug, thus putting project schedules at risk. Traditional debug techniques cannot always help to localize the issue. This whitepaper shows the benefits of debugging with ‘real-time trace’ hardware assistance, including how it can vastly reduce the amount of time needed to track down problems in the code, and introduces other benefits, such as hot-spot profiling and code coverage, offered by real-time trace systems.
James Campbell, CAE, Synopsys, Inc.; Valeriy Kazantsev, CAE, Synopsys, Inc.; Hugh O’Keefe, Engineering Director, Ashling Microsystems

Designing Application-Specific Processors for Wireless Baseband SoCs
Traditional architectures for wireless baseband applications are no longer adequate for next-generation modem standards. Supporting multiple, evolving standards in a single modem is only possible by using SDR techniques, which place increasing demands on performance and power consumption on the SoC. ASIP architectures enable full customization of a processor, which allows design teams to better optimize their design’s wireless baseband SoCs. This white paper describes how tool-based ASIP design methodologies automate the generation of the software tool chain, including an optimized software compiler, and the generation of RTL for ASIC and FPGA implementation, which enables rapid architecture exploration and trade-off analysis between performance, power and area.
Bo Wu, Technical Marketing Manager, Synopsys, Inc.

A Method to Quickly Assess the Analog Front-End Performance in Communication SoCs
This white paper outlines a simplified method to determine if the electrical characteristics of any given AFE are adequate for the targeted application such as broadband signal transceivers in the context of wireless or wireline connectivity, cellular communications and digital TV and radio broadcast. Additionally, it illustrates a tool to explore tradeoffs between relative performance and operating modes of different components to find the optimal performance, power, area and cost for SoCs.
Manuel Mota, Technical Marketing Manager, Synopsys, Inc.

ARC HS38: 消費電力と面積の制約が厳しい組込み機器での高速Linuxプロセッシングに最適なシングル/マルチコア(Linley Group社のホワイトペーパー)
Linuxなど仮想メモリーを使用する各種組込みオペレーティング・システムを実行する高性能な組込みSoCの設計者は、消費電力を従来と同等かそれ以下に抑えた上で、従来以上の性能を実現していかなければなりません。そのために必要な性能を提供してくれるプロセッサの多くは非常に消費電力が高く、一方で低消費電力のプロセッサは性能不足であるケースがしばしばです。The DesignWare ARC HS38マルチコア・プロセッサは、こうした組込みLinuxアプリケーション用に開発されたプロセッサで、メモリー管理ユニット(MMU)と高速二次キャッシュを搭載したCPUをシングル/デュアル/クワッドのコア構成で実装できます。本稿では、ARC HSプロセッサのアーキテクチャやARC HS38プロセッサに搭載されている新機能についてご説明します。
Tom R. Halfhill, Senior Analyst, The Linley Group

Meeting the USB IP Requirements of SoC Designs from 180-nm to 14/16-nm FinFET
USB’s ease-of-use and wide availability is belied by USB IP designers’ technical innovations. Without these innovations, USB could not be enabled in a broad range of process technologies ranging from 180-nm to the latest 14/16-nm FinFET technologies. This white paper addresses the five critical challenges facing designers of USB IP who need to keep pace with the process technology changes as well as the USB standard evolution.
Gervais Fong, Sr. USB Product Marketing Manager, Synopsys

クラウド・コンピューティング時代のネットワーク・ボトルネックを解消するVXLANベースのEthernet IP
インターネット・トラフィックの増大に対処するため、最近のクラウド・コンピューティング・データセンターでは、最適化されたEthernetIP上でネットワーク仮想化技術が利用されるようになっています。この驚異的なクラウド・コンピューティングの成長に伴い、Virtual Extensible LA(VXLAN)などの新しいネットワーク・オーバーレイ・プロトコルが登場しました。本稿では、VXLANによって得られるメリットの詳細、それによってネットワーク・インフラの制約によるボトルネックをいかに解消できるか、そしてEthernet IPの実装に与える影響について考察します。また、VXLANに対応したIPが、次世代のネットワーク仮想化SoCの開発においていかに重要な役割を果たすかについてもご説明します。
Ron DIGiuseppe, Sr. Strategic Marketing Manager, Synopsys




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